Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100416898	1			T1	1391		T2	1469		T3	450052
all_pins[1]	100416898	1			T1	1391		T2	1469		T3	450052
all_pins[2]	100416898	1			T1	1391		T2	1469		T3	450052

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300482923	1			T1	4161		T2	4211		T3	134681
values[0x1]	767771	1			T1	12		T2	196		T3	3342
transitions[0x0=>0x1]	765999	1			T1	12		T2	196		T3	3342
transitions[0x1=>0x0]	766014	1			T1	12		T2	196		T3	3342

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99912355	1			T1	1379		T2	1273		T3	446710
all_pins[0]	values[0x1]	504543	1			T1	12		T2	196		T3	3342
all_pins[0]	transitions[0x0=>0x1]	504533	1			T1	12		T2	196		T3	3342
all_pins[0]	transitions[0x1=>0x0]	6535	1			T33	2		T36	48		T18	35
all_pins[1]	values[0x0]	100410353	1			T1	1391		T2	1469		T3	450052
all_pins[1]	values[0x1]	6545	1			T33	2		T36	48		T18	35
all_pins[1]	transitions[0x0=>0x1]	6309	1			T33	2		T36	48		T18	35
all_pins[1]	transitions[0x1=>0x0]	256447	1			T19	993		T20	616		T43	357
all_pins[2]	values[0x0]	100160215	1			T1	1391		T2	1469		T3	450052
all_pins[2]	values[0x1]	256683	1			T19	993		T20	616		T43	357
all_pins[2]	transitions[0x0=>0x1]	255157	1			T19	992		T20	615		T43	357
all_pins[2]	transitions[0x1=>0x0]	503032	1			T1	12		T2	196		T3	3342