Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10780592 |
1 |
|
|
T1 |
1953 |
|
T2 |
4818 |
|
T3 |
47900 |
auto[1] |
10780543 |
1 |
|
|
T1 |
1953 |
|
T2 |
4818 |
|
T3 |
47900 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21323631 |
1 |
|
|
T1 |
3892 |
|
T2 |
9446 |
|
T3 |
93928 |
triple_byte_access |
78852 |
1 |
|
|
T1 |
6 |
|
T2 |
66 |
|
T3 |
620 |
halfword_access |
79524 |
1 |
|
|
T1 |
4 |
|
T2 |
60 |
|
T3 |
632 |
byte_access |
79128 |
1 |
|
|
T1 |
4 |
|
T2 |
64 |
|
T3 |
620 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10661840 |
1 |
|
|
T1 |
1946 |
|
T2 |
4723 |
|
T3 |
46964 |
auto[0] |
triple_byte_access |
39426 |
1 |
|
|
T1 |
3 |
|
T2 |
33 |
|
T3 |
310 |
auto[0] |
halfword_access |
39762 |
1 |
|
|
T1 |
2 |
|
T2 |
30 |
|
T3 |
316 |
auto[0] |
byte_access |
39564 |
1 |
|
|
T1 |
2 |
|
T2 |
32 |
|
T3 |
310 |
auto[1] |
word_access |
10661791 |
1 |
|
|
T1 |
1946 |
|
T2 |
4723 |
|
T3 |
46964 |
auto[1] |
triple_byte_access |
39426 |
1 |
|
|
T1 |
3 |
|
T2 |
33 |
|
T3 |
310 |
auto[1] |
halfword_access |
39762 |
1 |
|
|
T1 |
2 |
|
T2 |
30 |
|
T3 |
316 |
auto[1] |
byte_access |
39564 |
1 |
|
|
T1 |
2 |
|
T2 |
32 |
|
T3 |
310 |