Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 296 1 T140 4 T141 7 T142 7
all_values[1] 296 1 T140 4 T141 7 T142 7
all_values[2] 296 1 T140 4 T141 7 T142 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 492 1 T140 7 T141 8 T142 10
auto[1] 396 1 T140 5 T141 13 T142 11


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 398 1 T140 6 T141 10 T142 12
auto[1] 490 1 T140 6 T141 11 T142 9


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 527 1 T140 7 T141 13 T142 14
auto[1] 361 1 T140 5 T141 8 T142 7


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 66 1 T142 3 T181 3 T182 1
all_values[0] auto[0] auto[0] auto[1] 33 1 T140 1 T183 1 T184 1
all_values[0] auto[0] auto[1] auto[0] 41 1 T141 2 T142 4 T181 2
all_values[0] auto[0] auto[1] auto[1] 27 1 T141 2 T182 1 T185 1
all_values[0] auto[1] auto[0] auto[1] 77 1 T140 3 T141 2 T181 1
all_values[0] auto[1] auto[1] auto[1] 52 1 T141 1 T181 1 T185 2
all_values[1] auto[0] auto[0] auto[0] 94 1 T140 2 T141 2 T142 1
all_values[1] auto[0] auto[1] auto[0] 93 1 T140 1 T141 2 T142 3
all_values[1] auto[1] auto[0] auto[1] 59 1 T141 1 T142 1 T181 1
all_values[1] auto[1] auto[1] auto[1] 50 1 T140 1 T141 2 T142 2
all_values[2] auto[0] auto[0] auto[0] 55 1 T181 2 T176 1 T185 1
all_values[2] auto[0] auto[0] auto[1] 32 1 T141 1 T142 1 T176 1
all_values[2] auto[0] auto[1] auto[0] 49 1 T140 3 T141 4 T142 1
all_values[2] auto[0] auto[1] auto[1] 37 1 T142 1 T182 1 T176 1
all_values[2] auto[1] auto[0] auto[1] 76 1 T140 1 T141 2 T142 4
all_values[2] auto[1] auto[1] auto[1] 47 1 T181 1 T182 2 T185 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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