Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101454064	1			T1	45769		T3	14342		T32	311
all_values[1]	101454064	1			T1	45769		T3	14342		T32	311
all_values[2]	101454064	1			T1	45769		T3	14342		T32	311

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

668921

1

T1

309

T3

15

T32

83

auto[1]

303693271

1

T1

136998

T3

43011

T32

850

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

302823909

1

T1

135906

T3

42576

T32

888

auto[1]

1538283

1

T1

1401

T3

450

T32

45

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	197135	1			T1	192		T32	63		T33	4
all_values[0]	auto[0]	auto[1]	2292	1			T1	4		T32	6		T33	2
all_values[0]	auto[1]	auto[0]	100744168	1			T1	45110		T3	14192		T32	233
all_values[0]	auto[1]	auto[1]	510469	1			T1	463		T3	150		T32	9
all_values[1]	auto[0]	auto[0]	239776	1			T1	41		T3	14		T34	4
all_values[1]	auto[0]	auto[1]	1756	1			T1	6		T3	1		T34	2
all_values[1]	auto[1]	auto[0]	100701527	1			T1	45261		T3	14178		T32	296
all_values[1]	auto[1]	auto[1]	511005	1			T1	461		T3	149		T32	15
all_values[2]	auto[0]	auto[0]	226175	1			T1	59		T32	10		T33	4
all_values[2]	auto[0]	auto[1]	1787	1			T1	7		T32	4		T33	2
all_values[2]	auto[1]	auto[0]	100715128	1			T1	45243		T3	14192		T32	286
all_values[2]	auto[1]	auto[1]	510974	1			T1	460		T3	150		T32	11