Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
383994 |
1 |
|
|
T1 |
500 |
|
T3 |
200 |
|
T32 |
18 |
auto[1] |
314204 |
1 |
|
|
T1 |
226 |
|
T34 |
16 |
|
T7 |
312 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174458 |
1 |
|
|
T1 |
199 |
|
T3 |
42 |
|
T32 |
8 |
lower_val |
173485 |
1 |
|
|
T1 |
190 |
|
T3 |
49 |
|
T32 |
3 |
zero_val |
1880 |
1 |
|
|
T1 |
8 |
|
T3 |
1 |
|
T32 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
269928 |
1 |
|
|
T1 |
314 |
|
T3 |
114 |
|
T32 |
6 |
lower_val |
270632 |
1 |
|
|
T1 |
300 |
|
T3 |
86 |
|
T32 |
12 |
zero_val |
157638 |
1 |
|
|
T1 |
112 |
|
T34 |
6 |
|
T7 |
168 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
47620 |
1 |
|
|
T1 |
79 |
|
T3 |
26 |
|
T33 |
1 |
higher_val |
higher_val |
auto[1] |
19746 |
1 |
|
|
T1 |
17 |
|
T34 |
4 |
|
T7 |
18 |
higher_val |
lower_val |
auto[0] |
47832 |
1 |
|
|
T1 |
58 |
|
T3 |
16 |
|
T32 |
8 |
higher_val |
lower_val |
auto[1] |
19631 |
1 |
|
|
T1 |
18 |
|
T7 |
18 |
|
T15 |
21 |
higher_val |
zero_val |
auto[0] |
96 |
1 |
|
|
T82 |
1 |
|
T18 |
1 |
|
T51 |
1 |
higher_val |
zero_val |
auto[1] |
39533 |
1 |
|
|
T1 |
27 |
|
T7 |
54 |
|
T15 |
27 |
lower_val |
higher_val |
auto[0] |
47838 |
1 |
|
|
T1 |
70 |
|
T3 |
35 |
|
T32 |
2 |
lower_val |
higher_val |
auto[1] |
19439 |
1 |
|
|
T1 |
15 |
|
T34 |
3 |
|
T7 |
17 |
lower_val |
lower_val |
auto[0] |
47555 |
1 |
|
|
T1 |
62 |
|
T3 |
14 |
|
T32 |
1 |
lower_val |
lower_val |
auto[1] |
19702 |
1 |
|
|
T1 |
14 |
|
T34 |
1 |
|
T7 |
10 |
lower_val |
zero_val |
auto[0] |
104 |
1 |
|
|
T1 |
1 |
|
T34 |
1 |
|
T19 |
1 |
lower_val |
zero_val |
auto[1] |
38847 |
1 |
|
|
T1 |
28 |
|
T34 |
3 |
|
T7 |
33 |
zero_val |
higher_val |
auto[0] |
541 |
1 |
|
|
T1 |
2 |
|
T3 |
1 |
|
T33 |
1 |
zero_val |
higher_val |
auto[1] |
148 |
1 |
|
|
T15 |
1 |
|
T39 |
1 |
|
T40 |
1 |
zero_val |
lower_val |
auto[0] |
587 |
1 |
|
|
T1 |
3 |
|
T32 |
1 |
|
T36 |
1 |
zero_val |
lower_val |
auto[1] |
138 |
1 |
|
|
T1 |
1 |
|
T15 |
5 |
|
T39 |
3 |
zero_val |
zero_val |
auto[0] |
294 |
1 |
|
|
T1 |
1 |
|
T34 |
1 |
|
T67 |
1 |
zero_val |
zero_val |
auto[1] |
172 |
1 |
|
|
T1 |
1 |
|
T39 |
2 |
|
T124 |
1 |