Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101454064	1			T1	45769		T3	14342		T32	311
all_pins[1]	101454064	1			T1	45769		T3	14342		T32	311
all_pins[2]	101454064	1			T1	45769		T3	14342		T32	311

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	303533119	1			T1	134132		T3	42876		T32	924
values[0x1]	829073	1			T1	3175		T3	150		T32	9
transitions[0x0=>0x1]	826997	1			T1	3147		T3	150		T32	9
transitions[0x1=>0x0]	827025	1			T1	3147		T3	150		T32	9

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100943595	1			T1	45306		T3	14192		T32	302
all_pins[0]	values[0x1]	510469	1			T1	463		T3	150		T32	9
all_pins[0]	transitions[0x0=>0x1]	510458	1			T1	463		T3	150		T32	9
all_pins[0]	transitions[0x1=>0x0]	6174	1			T1	97		T38	32		T37	21
all_pins[1]	values[0x0]	101447879	1			T1	45672		T3	14342		T32	311
all_pins[1]	values[0x1]	6185	1			T1	97		T38	32		T37	21
all_pins[1]	transitions[0x0=>0x1]	6026	1			T1	87		T38	32		T37	21
all_pins[1]	transitions[0x1=>0x0]	312260	1			T1	2605		T7	1305		T15	1805
all_pins[2]	values[0x0]	101141645	1			T1	43154		T3	14342		T32	311
all_pins[2]	values[0x1]	312419	1			T1	2615		T7	1305		T15	1805
all_pins[2]	transitions[0x0=>0x1]	310513	1			T1	2597		T7	1305		T15	1793
all_pins[2]	transitions[0x1=>0x0]	508591	1			T1	445		T3	150		T32	9