Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	725	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5693	1			T1	35		T3	20		T35	19
len_601_800	13183	1			T1	66		T3	27		T35	33
len_401_600	8722	1			T1	55		T3	28		T35	18
len_201_400	16677	1			T1	20		T3	8		T35	8
len_65_200	74012	1			T1	46		T3	9		T35	3
len_min_for_xof_require_squeeze	993	1			T58	10		T39	10		T40	10
len_keccak_block_sizes[72]	744	1			T35	1		T58	5		T39	5
len_keccak_block_sizes[104]	764	1			T1	1		T58	5		T39	5
len_keccak_block_sizes[136]	746	1			T1	1		T58	5		T39	5
len_keccak_block_sizes[144]	285	1			T58	5		T39	5		T40	5
len_keccak_block_sizes[168]	286	1			T58	5		T39	5		T40	5
len_datapath_width	13968	1			T1	17		T3	1		T32	3
len_2_63	214280	1			T1	118		T3	5		T32	6
len_1	54	1			T7	1		T15	1		T16	1