Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11042329 |
1 |
|
|
T1 |
38637 |
|
T3 |
16140 |
|
T32 |
96 |
auto[1] |
11042329 |
1 |
|
|
T1 |
38637 |
|
T3 |
16140 |
|
T32 |
96 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21843338 |
1 |
|
|
T1 |
76886 |
|
T3 |
32138 |
|
T32 |
192 |
triple_byte_access |
80404 |
1 |
|
|
T1 |
154 |
|
T3 |
56 |
|
T35 |
38 |
halfword_access |
80650 |
1 |
|
|
T1 |
114 |
|
T3 |
44 |
|
T35 |
48 |
byte_access |
80266 |
1 |
|
|
T1 |
120 |
|
T3 |
42 |
|
T35 |
40 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10921669 |
1 |
|
|
T1 |
38443 |
|
T3 |
16069 |
|
T32 |
96 |
auto[0] |
triple_byte_access |
40202 |
1 |
|
|
T1 |
77 |
|
T3 |
28 |
|
T35 |
19 |
auto[0] |
halfword_access |
40325 |
1 |
|
|
T1 |
57 |
|
T3 |
22 |
|
T35 |
24 |
auto[0] |
byte_access |
40133 |
1 |
|
|
T1 |
60 |
|
T3 |
21 |
|
T35 |
20 |
auto[1] |
word_access |
10921669 |
1 |
|
|
T1 |
38443 |
|
T3 |
16069 |
|
T32 |
96 |
auto[1] |
triple_byte_access |
40202 |
1 |
|
|
T1 |
77 |
|
T3 |
28 |
|
T35 |
19 |
auto[1] |
halfword_access |
40325 |
1 |
|
|
T1 |
57 |
|
T3 |
22 |
|
T35 |
24 |
auto[1] |
byte_access |
40133 |
1 |
|
|
T1 |
60 |
|
T3 |
21 |
|
T35 |
20 |