Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.35	97.91	92.65	99.89	77.46	95.59	99.05	97.88

Total test records in report: 1253

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html

T1252	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3481261968			Jun 04 12:45:50 PM PDT 24	Jun 04 12:45:53 PM PDT 24	46809300 ps
T96	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1279037385			Jun 04 12:46:07 PM PDT 24	Jun 04 12:46:09 PM PDT 24	69535906 ps
T1253	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1843536950			Jun 04 12:45:50 PM PDT 24	Jun 04 12:45:53 PM PDT 24	59427788 ps

Test location	/workspace/coverage/default/25.kmac_stress_all.2188662893
Short name	T1
Test name
Test status
Simulation time	151361081966 ps
CPU time	895.58 seconds
Started	Jun 04 02:28:52 PM PDT 24
Finished	Jun 04 02:43:48 PM PDT 24
Peak memory	334360 kb
Host	smart-fac64ab7-875c-4a4c-924c-b5e27aed6b98
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2188662893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.2188662893 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_stress_all/latest

Test location	/workspace/coverage/default/4.kmac_sec_cm.66084526
Short name	T13
Test name
Test status
Simulation time	31263735703 ps
CPU time	79.27 seconds
Started	Jun 04 02:23:51 PM PDT 24
Finished	Jun 04 02:25:11 PM PDT 24
Peak memory	266280 kb
Host	smart-cf6cd159-3f8c-40ff-ae90-55c9126bbfb7
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66084526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.66084526 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2956278447
Short name	T127
Test name
Test status
Simulation time	477470326 ps
CPU time	3.02 seconds
Started	Jun 04 12:46:14 PM PDT 24
Finished	Jun 04 12:46:18 PM PDT 24
Peak memory	216080 kb
Host	smart-395e2942-b09e-4ae9-8612-9c5d0f055d5e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956278447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2956 278447 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/21.kmac_stress_all_with_rand_reset.2918805553
Short name	T15
Test name
Test status
Simulation time	95423344218 ps
CPU time	2059.71 seconds
Started	Jun 04 02:27:45 PM PDT 24
Finished	Jun 04 03:02:06 PM PDT 24
Peak memory	382492 kb
Host	smart-d16816a3-973f-4b3e-9f04-f13fd44250e5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2918805553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all_with_rand_reset.2918805553 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.kmac_lc_escalation.1843448070
Short name	T29
Test name
Test status
Simulation time	55485532 ps
CPU time	1.65 seconds
Started	Jun 04 02:25:30 PM PDT 24
Finished	Jun 04 02:25:32 PM PDT 24
Peak memory	227384 kb
Host	smart-4c8df6c0-f534-4d5b-84d5-c448523c8fe4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1843448070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.1843448070 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/13.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/44.kmac_key_error.1045397927
Short name	T118
Test name
Test status
Simulation time	586910277 ps
CPU time	4.65 seconds
Started	Jun 04 02:36:44 PM PDT 24
Finished	Jun 04 02:36:49 PM PDT 24
Peak memory	223788 kb
Host	smart-e9defce6-24dd-467d-a646-554e0e604be4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1045397927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.1045397927 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_key_error/latest

Test location	/workspace/coverage/default/20.kmac_error.375310055
Short name	T21
Test name
Test status
Simulation time	21350905140 ps
CPU time	347.7 seconds
Started	Jun 04 02:27:23 PM PDT 24
Finished	Jun 04 02:33:11 PM PDT 24
Peak memory	268484 kb
Host	smart-99006c66-5aa1-4efd-870c-d5d933b0ad02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375310055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.375310055 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_error/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3615251212
Short name	T86
Test name
Test status
Simulation time	158819512 ps
CPU time	1.42 seconds
Started	Jun 04 12:46:18 PM PDT 24
Finished	Jun 04 12:46:21 PM PDT 24
Peak memory	217308 kb
Host	smart-38dbcb08-0582-430f-979a-9a6b4817f8aa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615251212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg _errors.3615251212 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/default/27.kmac_lc_escalation.3307998999
Short name	T14
Test name
Test status
Simulation time	73244072 ps
CPU time	1.43 seconds
Started	Jun 04 02:29:33 PM PDT 24
Finished	Jun 04 02:29:35 PM PDT 24
Peak memory	227228 kb
Host	smart-b0746394-76de-4caa-870b-25795867fc29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3307998999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.3307998999 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/27.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/5.kmac_entropy_ready_error.909781266
Short name	T583
Test name
Test status
Simulation time	3773443324 ps
CPU time	53.93 seconds
Started	Jun 04 02:24:00 PM PDT 24
Finished	Jun 04 02:24:54 PM PDT 24
Peak memory	227504 kb
Host	smart-0174894d-9930-4d6a-9046-27f5ac243b4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=909781266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.909781266 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspace/5.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_intr_test.4218634529
Short name	T131
Test name
Test status
Simulation time	11446350 ps
CPU time	0.81 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:12 PM PDT 24
Peak memory	215592 kb
Host	smart-e9fb1da4-8252-41b1-b896-7e97ea3bff2a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218634529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.4218634529 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_intr_test/latest

Test location	/workspace/coverage/default/0.kmac_edn_timeout_error.270452506
Short name	T335
Test name
Test status
Simulation time	47842917 ps
CPU time	0.9 seconds
Started	Jun 04 02:23:18 PM PDT 24
Finished	Jun 04 02:23:19 PM PDT 24
Peak memory	222400 kb
Host	smart-84e48495-ab5e-472b-8458-702f10d13bb5
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=270452506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.270452506 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/40.kmac_lc_escalation.4158086524
Short name	T61
Test name
Test status
Simulation time	905767848 ps
CPU time	6.14 seconds
Started	Jun 04 02:35:02 PM PDT 24
Finished	Jun 04 02:35:09 PM PDT 24
Peak memory	227504 kb
Host	smart-061a3ef0-d574-4f41-8b67-19c0a05093d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4158086524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.4158086524 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/40.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/11.kmac_entropy_mode_error.3230294145
Short name	T516
Test name
Test status
Simulation time	108109346 ps
CPU time	1.13 seconds
Started	Jun 04 02:25:03 PM PDT 24
Finished	Jun 04 02:25:05 PM PDT 24
Peak memory	222552 kb
Host	smart-48156930-7d90-40dd-a7e8-d8e1dc44e614
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3230294145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.3230294145 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/1.kmac_lc_escalation.800158692
Short name	T42
Test name
Test status
Simulation time	63562940 ps
CPU time	1.35 seconds
Started	Jun 04 02:23:37 PM PDT 24
Finished	Jun 04 02:23:39 PM PDT 24
Peak memory	227132 kb
Host	smart-7a120bc8-b7e0-4100-b3df-66cb794f52bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=800158692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.800158692 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/20.kmac_lc_escalation.2007159720
Short name	T438
Test name
Test status
Simulation time	1417361175 ps
CPU time	17.85 seconds
Started	Jun 04 02:27:21 PM PDT 24
Finished	Jun 04 02:27:39 PM PDT 24
Peak memory	235628 kb
Host	smart-007d5ca8-e95e-4852-aef7-4530907df9c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2007159720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.2007159720 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/20.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_shake_256.4018725807
Short name	T40
Test name
Test status
Simulation time	457414867794 ps
CPU time	5225.79 seconds
Started	Jun 04 02:29:00 PM PDT 24
Finished	Jun 04 03:56:07 PM PDT 24
Peak memory	556516 kb
Host	smart-43a41e0d-f307-498b-9088-914a49b84c04
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4018725807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.4018725807 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.981225933
Short name	T99
Test name
Test status
Simulation time	212761291 ps
CPU time	1.36 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:12 PM PDT 24
Peak memory	216248 kb
Host	smart-c58d17de-f446-4f7e-a3e4-d75052d5353a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981225933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_ errors.981225933 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3246106268
Short name	T174
Test name
Test status
Simulation time	187874484 ps
CPU time	4.48 seconds
Started	Jun 04 12:45:59 PM PDT 24
Finished	Jun 04 12:46:05 PM PDT 24
Peak memory	216012 kb
Host	smart-09b88872-6335-4c51-991d-c119f5ea8441
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246106268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.32461 06268 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2897561003
Short name	T141
Test name
Test status
Simulation time	219560955 ps
CPU time	1.3 seconds
Started	Jun 04 12:45:49 PM PDT 24
Finished	Jun 04 12:45:52 PM PDT 24
Peak memory	215972 kb
Host	smart-159bcfa1-5398-41fc-b7a5-82031ae18b02
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897561003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia l_access.2897561003 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_partial_access/latest

Test location	/workspace/coverage/default/11.kmac_lc_escalation.713583050
Short name	T643
Test name
Test status
Simulation time	93347370 ps
CPU time	1.22 seconds
Started	Jun 04 02:25:05 PM PDT 24
Finished	Jun 04 02:25:08 PM PDT 24
Peak memory	227264 kb
Host	smart-ea141735-3158-462d-826d-a289443ac9c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=713583050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.713583050 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/11.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/16.kmac_lc_escalation.3085004071
Short name	T77
Test name
Test status
Simulation time	31481964 ps
CPU time	1.24 seconds
Started	Jun 04 02:26:32 PM PDT 24
Finished	Jun 04 02:26:34 PM PDT 24
Peak memory	227236 kb
Host	smart-bfcb81f9-6057-43b0-8652-e1301178ea3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085004071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.3085004071 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/16.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/23.kmac_lc_escalation.3001659546
Short name	T50
Test name
Test status
Simulation time	550457788 ps
CPU time	24.73 seconds
Started	Jun 04 02:28:12 PM PDT 24
Finished	Jun 04 02:28:38 PM PDT 24
Peak memory	234960 kb
Host	smart-a25c8604-d303-47e2-94df-dc2948b52291
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3001659546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.3001659546 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/23.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/1.kmac_alert_test.209668908
Short name	T186
Test name
Test status
Simulation time	58105622 ps
CPU time	0.89 seconds
Started	Jun 04 02:23:34 PM PDT 24
Finished	Jun 04 02:23:36 PM PDT 24
Peak memory	218932 kb
Host	smart-05f36ee4-5ec3-4a21-b399-22606a70a11d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209668908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.209668908 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/26.kmac_intr_test.315645471
Short name	T164
Test name
Test status
Simulation time	15565443 ps
CPU time	0.8 seconds
Started	Jun 04 12:46:15 PM PDT 24
Finished	Jun 04 12:46:16 PM PDT 24
Peak memory	215672 kb
Host	smart-b34382be-2b96-4ae6-a4ef-28a18e7867dd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315645471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.315645471 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_intr_test/latest

Test location	/workspace/coverage/default/11.kmac_entropy_refresh.4281237097
Short name	T69
Test name
Test status
Simulation time	4589203088 ps
CPU time	78.93 seconds
Started	Jun 04 02:25:05 PM PDT 24
Finished	Jun 04 02:26:25 PM PDT 24
Peak memory	232976 kb
Host	smart-b9f9d003-74c1-4120-8b39-e4d5b1c309de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4281237097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.4281237097 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/11.kmac_entropy_refresh/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.963947746
Short name	T95
Test name
Test status
Simulation time	28513949 ps
CPU time	0.97 seconds
Started	Jun 04 12:46:22 PM PDT 24
Finished	Jun 04 12:46:24 PM PDT 24
Peak memory	216076 kb
Host	smart-a00ec4b4-2387-4077-bb84-302a0a0c15ab
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963947746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_ errors.963947746 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/default/18.kmac_error.404311256
Short name	T7
Test name
Test status
Simulation time	45812233745 ps
CPU time	400.84 seconds
Started	Jun 04 02:26:56 PM PDT 24
Finished	Jun 04 02:33:37 PM PDT 24
Peak memory	256932 kb
Host	smart-df2f4063-434f-450f-ae1f-645c757975e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=404311256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.404311256 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_error/latest

Test location	/workspace/coverage/default/37.kmac_key_error.4037935186
Short name	T106
Test name
Test status
Simulation time	6985897581 ps
CPU time	9.07 seconds
Started	Jun 04 02:33:51 PM PDT 24
Finished	Jun 04 02:34:01 PM PDT 24
Peak memory	225996 kb
Host	smart-513965dc-76e8-4190-8698-75cb819db1c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4037935186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.4037935186 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_key_error/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1761496366
Short name	T170
Test name
Test status
Simulation time	401745948 ps
CPU time	5.26 seconds
Started	Jun 04 12:45:49 PM PDT 24
Finished	Jun 04 12:45:56 PM PDT 24
Peak memory	216108 kb
Host	smart-55eda221-3eec-415a-b3ce-bcb5d2f0e8b7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761496366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.17614 96366 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/38.kmac_sideload.2893702904
Short name	T104
Test name
Test status
Simulation time	5310667116 ps
CPU time	436.06 seconds
Started	Jun 04 02:34:00 PM PDT 24
Finished	Jun 04 02:41:17 PM PDT 24
Peak memory	254836 kb
Host	smart-aa4917ee-490f-46ce-8c2f-36ba44001a83
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893702904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2893702904 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_sideload/latest

Test location	/workspace/coverage/default/14.kmac_entropy_refresh.3053222546
Short name	T63
Test name
Test status
Simulation time	11015069205 ps
CPU time	217.69 seconds
Started	Jun 04 02:25:46 PM PDT 24
Finished	Jun 04 02:29:24 PM PDT 24
Peak memory	240800 kb
Host	smart-7bc79732-e1b1-423d-bdca-cde187458a70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3053222546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.3053222546 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/14.kmac_entropy_refresh/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.9121507
Short name	T171
Test name
Test status
Simulation time	259321854 ps
CPU time	5.18 seconds
Started	Jun 04 12:46:08 PM PDT 24
Finished	Jun 04 12:46:15 PM PDT 24
Peak memory	215988 kb
Host	smart-4b78c4aa-1fac-4151-b136-8e4177029061
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9121507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.9121507 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3046665573
Short name	T177
Test name
Test status
Simulation time	1005885134 ps
CPU time	5.74 seconds
Started	Jun 04 12:46:16 PM PDT 24
Finished	Jun 04 12:46:22 PM PDT 24
Peak memory	216156 kb
Host	smart-6a5d565a-1576-4c6c-9356-abe709b12145
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046665573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3046 665573 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2620723229
Short name	T125
Test name
Test status
Simulation time	45608653 ps
CPU time	0.82 seconds
Started	Jun 04 12:45:44 PM PDT 24
Finished	Jun 04 12:45:46 PM PDT 24
Peak memory	215844 kb
Host	smart-ba503428-a7f7-4cbc-883c-fe7d5a2c9993
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620723229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_ errors.2620723229 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/default/18.kmac_stress_all_with_rand_reset.1686217817
Short name	T78
Test name
Test status
Simulation time	40298187054 ps
CPU time	682.13 seconds
Started	Jun 04 02:26:56 PM PDT 24
Finished	Jun 04 02:38:19 PM PDT 24
Peak memory	276436 kb
Host	smart-40c4cb35-76c2-4af1-8b7d-1df5c277b2f9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1686217817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all_with_rand_reset.1686217817 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.3327302011
Short name	T1167
Test name
Test status
Simulation time	830064626 ps
CPU time	5.11 seconds
Started	Jun 04 12:45:43 PM PDT 24
Finished	Jun 04 12:45:49 PM PDT 24
Peak memory	215932 kb
Host	smart-98dd051d-e264-487f-86a4-ad24665846b4
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327302011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3327302 011 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.4199931649
Short name	T1123
Test name
Test status
Simulation time	316095515 ps
CPU time	8.14 seconds
Started	Jun 04 12:45:46 PM PDT 24
Finished	Jun 04 12:45:55 PM PDT 24
Peak memory	215924 kb
Host	smart-ce3d0632-0806-435f-a6e0-e97a4b4aeddc
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199931649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.4199931 649 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1711535180
Short name	T1114
Test name
Test status
Simulation time	30276401 ps
CPU time	1.14 seconds
Started	Jun 04 12:45:45 PM PDT 24
Finished	Jun 04 12:45:47 PM PDT 24
Peak memory	215868 kb
Host	smart-814f17ff-d4ee-4080-b32f-0d9ec00fecc8
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711535180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1711535 180 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.4068262106
Short name	T1200
Test name
Test status
Simulation time	126040532 ps
CPU time	2.29 seconds
Started	Jun 04 12:45:49 PM PDT 24
Finished	Jun 04 12:45:53 PM PDT 24
Peak memory	220820 kb
Host	smart-5acb5135-c096-44c6-9656-de0fd1cda2d4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068262106 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.4068262106 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.943117700
Short name	T1129
Test name
Test status
Simulation time	14741350 ps
CPU time	0.95 seconds
Started	Jun 04 12:45:49 PM PDT 24
Finished	Jun 04 12:45:51 PM PDT 24
Peak memory	215808 kb
Host	smart-b32c93cf-ce21-48d2-ac4e-f5ed5c3c19ef
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943117700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.943117700 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_intr_test.2222524859
Short name	T1197
Test name
Test status
Simulation time	15363998 ps
CPU time	0.81 seconds
Started	Jun 04 12:45:49 PM PDT 24
Finished	Jun 04 12:45:52 PM PDT 24
Peak memory	215800 kb
Host	smart-0b03d1d1-f2bd-44e7-9ec7-3c41f4edf8f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222524859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2222524859 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3684849465
Short name	T139
Test name
Test status
Simulation time	49872410 ps
CPU time	1.44 seconds
Started	Jun 04 12:45:40 PM PDT 24
Finished	Jun 04 12:45:44 PM PDT 24
Peak memory	215992 kb
Host	smart-df725505-2f27-462d-b00d-6e0c43122674
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684849465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia l_access.3684849465 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.522172079
Short name	T1137
Test name
Test status
Simulation time	12545674 ps
CPU time	0.74 seconds
Started	Jun 04 12:45:41 PM PDT 24
Finished	Jun 04 12:45:43 PM PDT 24
Peak memory	215776 kb
Host	smart-3c59a359-4268-4588-b37e-5c6838f25232
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522172079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.522172079 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1437427015
Short name	T1095
Test name
Test status
Simulation time	35551959 ps
CPU time	1.4 seconds
Started	Jun 04 12:45:50 PM PDT 24
Finished	Jun 04 12:45:52 PM PDT 24
Peak memory	215980 kb
Host	smart-6f29d22c-b8de-4850-a1c9-a54bab81d66b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437427015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr _outstanding.1437427015 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2995981731
Short name	T94
Test name
Test status
Simulation time	34476114 ps
CPU time	1.81 seconds
Started	Jun 04 12:45:44 PM PDT 24
Finished	Jun 04 12:45:47 PM PDT 24
Peak memory	218408 kb
Host	smart-d578ce2f-787f-42fe-9817-cafcffdcc814
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995981731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac _shadow_reg_errors_with_csr_rw.2995981731 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.408506725
Short name	T1116
Test name
Test status
Simulation time	933896273 ps
CPU time	3.63 seconds
Started	Jun 04 12:45:44 PM PDT 24
Finished	Jun 04 12:45:49 PM PDT 24
Peak memory	216132 kb
Host	smart-3080d5a1-ecc9-4fb2-a072-a93b1202ec11
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408506725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.408506725 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.989016426
Short name	T1135
Test name
Test status
Simulation time	200522170 ps
CPU time	4.98 seconds
Started	Jun 04 12:45:48 PM PDT 24
Finished	Jun 04 12:45:55 PM PDT 24
Peak memory	215924 kb
Host	smart-abe3ae8d-084c-43ed-9284-ca915fed82c0
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989016426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.98901642 6 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.2644112045
Short name	T1213
Test name
Test status
Simulation time	4003145048 ps
CPU time	19.88 seconds
Started	Jun 04 12:45:50 PM PDT 24
Finished	Jun 04 12:46:11 PM PDT 24
Peak memory	216000 kb
Host	smart-a814257a-fcbc-4d65-b59c-568ef90c29c7
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644112045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2644112 045 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2162256731
Short name	T1173
Test name
Test status
Simulation time	30490230 ps
CPU time	1.01 seconds
Started	Jun 04 12:45:48 PM PDT 24
Finished	Jun 04 12:45:50 PM PDT 24
Peak memory	215712 kb
Host	smart-06d967cd-9a05-4444-9dc8-3f2fafebd06f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162256731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2162256 731 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2176818723
Short name	T1153
Test name
Test status
Simulation time	57930218 ps
CPU time	1.81 seconds
Started	Jun 04 12:45:49 PM PDT 24
Finished	Jun 04 12:45:52 PM PDT 24
Peak memory	220552 kb
Host	smart-119f266c-7595-4773-bfd2-0471791e7039
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176818723 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.2176818723 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.3925187036
Short name	T1090
Test name
Test status
Simulation time	51078230 ps
CPU time	1.04 seconds
Started	Jun 04 12:45:50 PM PDT 24
Finished	Jun 04 12:45:52 PM PDT 24
Peak memory	215700 kb
Host	smart-20a35526-151e-4bb4-b870-e5f9e5c21be4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925187036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.3925187036 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_intr_test.408203115
Short name	T1208
Test name
Test status
Simulation time	75270172 ps
CPU time	0.89 seconds
Started	Jun 04 12:45:48 PM PDT 24
Finished	Jun 04 12:45:51 PM PDT 24
Peak memory	215744 kb
Host	smart-525a2c94-f845-41d9-86e6-3928a571d94c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408203115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.408203115 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.2790449682
Short name	T1237
Test name
Test status
Simulation time	15361533 ps
CPU time	0.75 seconds
Started	Jun 04 12:45:57 PM PDT 24
Finished	Jun 04 12:45:59 PM PDT 24
Peak memory	215748 kb
Host	smart-ede415b2-8be9-44a4-aebe-3541d0d4dfd7
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790449682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.2790449682 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.580383348
Short name	T1112
Test name
Test status
Simulation time	90492128 ps
CPU time	1.46 seconds
Started	Jun 04 12:45:49 PM PDT 24
Finished	Jun 04 12:45:52 PM PDT 24
Peak memory	215980 kb
Host	smart-39223628-e3a2-4066-b319-aa916d34ef4b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580383348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_ outstanding.580383348 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3481261968
Short name	T1252
Test name
Test status
Simulation time	46809300 ps
CPU time	1.18 seconds
Started	Jun 04 12:45:50 PM PDT 24
Finished	Jun 04 12:45:53 PM PDT 24
Peak memory	215988 kb
Host	smart-a2cb655b-3327-4c37-8f7a-5929c55bb843
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481261968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_ errors.3481261968 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.783693832
Short name	T1224
Test name
Test status
Simulation time	138534739 ps
CPU time	2.98 seconds
Started	Jun 04 12:45:50 PM PDT 24
Finished	Jun 04 12:45:54 PM PDT 24
Peak memory	218428 kb
Host	smart-1fc32298-924c-4814-89f0-9439328b7b47
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783693832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_ shadow_reg_errors_with_csr_rw.783693832 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.3243395610
Short name	T1251
Test name
Test status
Simulation time	147927433 ps
CPU time	3.61 seconds
Started	Jun 04 12:45:47 PM PDT 24
Finished	Jun 04 12:45:51 PM PDT 24
Peak memory	216120 kb
Host	smart-8939fc24-1f4e-492f-98a6-ee69c11d436a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243395610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3243395610 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.128458272
Short name	T169
Test name
Test status
Simulation time	727961720 ps
CPU time	5.08 seconds
Started	Jun 04 12:45:48 PM PDT 24
Finished	Jun 04 12:45:54 PM PDT 24
Peak memory	215988 kb
Host	smart-8be18957-9179-4c2c-ae73-23a94c93aff1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128458272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.128458 272 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3073393823
Short name	T1113
Test name
Test status
Simulation time	164686765 ps
CPU time	2.43 seconds
Started	Jun 04 12:46:06 PM PDT 24
Finished	Jun 04 12:46:10 PM PDT 24
Peak memory	220688 kb
Host	smart-d842de99-b0a3-489e-8ca3-e9d15cc88784
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073393823 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.3073393823 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.1697832722
Short name	T1091
Test name
Test status
Simulation time	37527473 ps
CPU time	0.98 seconds
Started	Jun 04 12:46:07 PM PDT 24
Finished	Jun 04 12:46:09 PM PDT 24
Peak memory	215828 kb
Host	smart-c0673d32-64d2-4722-bd41-192939534a4d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697832722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1697832722 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_intr_test.2106698286
Short name	T1236
Test name
Test status
Simulation time	15737926 ps
CPU time	0.82 seconds
Started	Jun 04 12:46:12 PM PDT 24
Finished	Jun 04 12:46:14 PM PDT 24
Peak memory	215756 kb
Host	smart-08485af7-ea4d-470f-8a20-ed1a658b88d4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106698286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.2106698286 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.298204594
Short name	T1196
Test name
Test status
Simulation time	136944887 ps
CPU time	2.19 seconds
Started	Jun 04 12:46:08 PM PDT 24
Finished	Jun 04 12:46:13 PM PDT 24
Peak memory	216016 kb
Host	smart-ecdf3dd4-de7d-4e15-87f9-0e4bd454a7e3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298204594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr _outstanding.298204594 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3226657525
Short name	T1217
Test name
Test status
Simulation time	159266362 ps
CPU time	1.23 seconds
Started	Jun 04 12:46:04 PM PDT 24
Finished	Jun 04 12:46:06 PM PDT 24
Peak memory	216584 kb
Host	smart-b4165477-a26e-42ae-90df-15be2484fe0b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226657525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg _errors.3226657525 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1399234800
Short name	T1215
Test name
Test status
Simulation time	55587045 ps
CPU time	1.69 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:13 PM PDT 24
Peak memory	215972 kb
Host	smart-52eb2d02-f5f9-4e3e-922b-a9648bb551ca
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399234800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma c_shadow_reg_errors_with_csr_rw.1399234800 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.3021483157
Short name	T1226
Test name
Test status
Simulation time	33450862 ps
CPU time	1.77 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:13 PM PDT 24
Peak memory	215972 kb
Host	smart-862a5168-8892-4b87-8ea2-82dccd392dda
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021483157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.3021483157 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.929747416
Short name	T172
Test name
Test status
Simulation time	195975872 ps
CPU time	2.39 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:13 PM PDT 24
Peak memory	216060 kb
Host	smart-92e288ab-5c5d-4497-b56e-c009cc1dc7d5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929747416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.92974 7416 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.4213652593
Short name	T1148
Test name
Test status
Simulation time	24663459 ps
CPU time	1.72 seconds
Started	Jun 04 12:46:12 PM PDT 24
Finished	Jun 04 12:46:15 PM PDT 24
Peak memory	217332 kb
Host	smart-4b10a058-c440-43c2-a5b1-20226364ddc0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213652593 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.4213652593 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.2614374005
Short name	T1163
Test name
Test status
Simulation time	26269982 ps
CPU time	0.95 seconds
Started	Jun 04 12:46:08 PM PDT 24
Finished	Jun 04 12:46:11 PM PDT 24
Peak memory	215680 kb
Host	smart-9f83c043-a193-40d8-ba62-bd318305f5fd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614374005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2614374005 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_intr_test.1341804675
Short name	T1239
Test name
Test status
Simulation time	11660221 ps
CPU time	0.81 seconds
Started	Jun 04 12:46:08 PM PDT 24
Finished	Jun 04 12:46:10 PM PDT 24
Peak memory	215708 kb
Host	smart-54eb9ce4-4ebf-4c21-b415-0d23084cdd37
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341804675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.1341804675 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1631770920
Short name	T1225
Test name
Test status
Simulation time	547101435 ps
CPU time	2.93 seconds
Started	Jun 04 12:46:08 PM PDT 24
Finished	Jun 04 12:46:13 PM PDT 24
Peak memory	215948 kb
Host	smart-1cfbb085-1bea-40e4-9488-cccd9d9e57ab
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631770920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs r_outstanding.1631770920 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1279037385
Short name	T96
Test name
Test status
Simulation time	69535906 ps
CPU time	1.32 seconds
Started	Jun 04 12:46:07 PM PDT 24
Finished	Jun 04 12:46:09 PM PDT 24
Peak memory	216272 kb
Host	smart-0ba1b407-30f2-4d31-a7b2-6dbaee0c80cd
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279037385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg _errors.1279037385 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.4292330164
Short name	T1107
Test name
Test status
Simulation time	364409234 ps
CPU time	2.53 seconds
Started	Jun 04 12:46:08 PM PDT 24
Finished	Jun 04 12:46:12 PM PDT 24
Peak memory	218332 kb
Host	smart-3dad0179-2df7-47d1-9ebb-07a6cf7f10b1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292330164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma c_shadow_reg_errors_with_csr_rw.4292330164 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.2343963091
Short name	T1164
Test name
Test status
Simulation time	22827468 ps
CPU time	1.45 seconds
Started	Jun 04 12:46:11 PM PDT 24
Finished	Jun 04 12:46:14 PM PDT 24
Peak memory	216072 kb
Host	smart-81e4f079-dcae-4f76-ad7f-314bea8a997a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343963091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2343963091 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.4154997802
Short name	T178
Test name
Test status
Simulation time	426598995 ps
CPU time	2.89 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:14 PM PDT 24
Peak memory	216156 kb
Host	smart-06c94b86-843e-4cf9-978f-f08e9e73468f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154997802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.4154 997802 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2725957918
Short name	T1134
Test name
Test status
Simulation time	304678673 ps
CPU time	2.51 seconds
Started	Jun 04 12:46:08 PM PDT 24
Finished	Jun 04 12:46:12 PM PDT 24
Peak memory	221176 kb
Host	smart-75c9f48d-2b87-4098-b997-9ba74166f501
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725957918 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.2725957918 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.4167793827
Short name	T1171
Test name
Test status
Simulation time	14037027 ps
CPU time	1 seconds
Started	Jun 04 12:46:08 PM PDT 24
Finished	Jun 04 12:46:10 PM PDT 24
Peak memory	215724 kb
Host	smart-d49e6be9-56bd-461c-9c89-e342dfa62aec
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167793827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.4167793827 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.4013580151
Short name	T1154
Test name
Test status
Simulation time	232065421 ps
CPU time	1.73 seconds
Started	Jun 04 12:46:10 PM PDT 24
Finished	Jun 04 12:46:14 PM PDT 24
Peak memory	216104 kb
Host	smart-ea43cde6-2259-47e4-b53d-32f34cc3b316
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013580151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs r_outstanding.4013580151 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1343292772
Short name	T1097
Test name
Test status
Simulation time	178594614 ps
CPU time	0.9 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:12 PM PDT 24
Peak memory	215776 kb
Host	smart-3e2b667d-2208-4c7c-b25e-3a44d8df238a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343292772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg _errors.1343292772 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.307845976
Short name	T1242
Test name
Test status
Simulation time	147736628 ps
CPU time	2.07 seconds
Started	Jun 04 12:46:08 PM PDT 24
Finished	Jun 04 12:46:13 PM PDT 24
Peak memory	219632 kb
Host	smart-29a54538-ab6b-48f3-aece-d194c2cc25ee
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307845976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac _shadow_reg_errors_with_csr_rw.307845976 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.2052262062
Short name	T1178
Test name
Test status
Simulation time	103233890 ps
CPU time	1.57 seconds
Started	Jun 04 12:46:07 PM PDT 24
Finished	Jun 04 12:46:09 PM PDT 24
Peak memory	216144 kb
Host	smart-558edeb6-79d2-472c-8095-25c209ad87c7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052262062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2052262062 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3753248799
Short name	T1155
Test name
Test status
Simulation time	577295226 ps
CPU time	4.72 seconds
Started	Jun 04 12:46:11 PM PDT 24
Finished	Jun 04 12:46:18 PM PDT 24
Peak memory	216040 kb
Host	smart-cee462e3-d18f-4e64-b115-975c91c15121
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753248799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.3753 248799 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2885006559
Short name	T1221
Test name
Test status
Simulation time	63016573 ps
CPU time	2.22 seconds
Started	Jun 04 12:46:07 PM PDT 24
Finished	Jun 04 12:46:11 PM PDT 24
Peak memory	222224 kb
Host	smart-26ecc3d7-6145-4492-b453-dcc365457f88
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885006559 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.2885006559 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.3096599271
Short name	T1158
Test name
Test status
Simulation time	87728447 ps
CPU time	1.15 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:12 PM PDT 24
Peak memory	215920 kb
Host	smart-3e008385-b4e4-41cb-833a-dadaa624601d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096599271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.3096599271 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_intr_test.796637946
Short name	T1120
Test name
Test status
Simulation time	18616669 ps
CPU time	0.82 seconds
Started	Jun 04 12:46:12 PM PDT 24
Finished	Jun 04 12:46:15 PM PDT 24
Peak memory	215748 kb
Host	smart-15f99585-414d-4f40-bd0d-0fd576e4f49d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796637946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.796637946 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.4235142485
Short name	T1209
Test name
Test status
Simulation time	97460298 ps
CPU time	1.61 seconds
Started	Jun 04 12:46:08 PM PDT 24
Finished	Jun 04 12:46:11 PM PDT 24
Peak memory	216104 kb
Host	smart-6cbb9073-fd84-4d42-8647-66e92aaa7768
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235142485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs r_outstanding.4235142485 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.538939501
Short name	T100
Test name
Test status
Simulation time	23334008 ps
CPU time	1.12 seconds
Started	Jun 04 12:46:08 PM PDT 24
Finished	Jun 04 12:46:10 PM PDT 24
Peak memory	216416 kb
Host	smart-be7e74b9-3dc5-48e9-8fdf-1f2683b66897
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538939501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_ errors.538939501 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3596616151
Short name	T1248
Test name
Test status
Simulation time	36496787 ps
CPU time	1.82 seconds
Started	Jun 04 12:46:07 PM PDT 24
Finished	Jun 04 12:46:10 PM PDT 24
Peak memory	219584 kb
Host	smart-29189c71-7ce1-4f2e-8972-8caab367615c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596616151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma c_shadow_reg_errors_with_csr_rw.3596616151 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.3604708261
Short name	T1103
Test name
Test status
Simulation time	443890432 ps
CPU time	2.95 seconds
Started	Jun 04 12:46:08 PM PDT 24
Finished	Jun 04 12:46:13 PM PDT 24
Peak memory	216136 kb
Host	smart-cbde9d44-7dee-47a2-a1fe-1297d4c295ba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604708261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.3604708261 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.322309269
Short name	T1156
Test name
Test status
Simulation time	68207920 ps
CPU time	2.55 seconds
Started	Jun 04 12:46:08 PM PDT 24
Finished	Jun 04 12:46:12 PM PDT 24
Peak memory	216172 kb
Host	smart-2b7a4ac0-42bd-4e4b-9972-0b923ab80430
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322309269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.32230 9269 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1479296245
Short name	T1185
Test name
Test status
Simulation time	48448319 ps
CPU time	1.64 seconds
Started	Jun 04 12:46:10 PM PDT 24
Finished	Jun 04 12:46:14 PM PDT 24
Peak memory	219260 kb
Host	smart-b998893b-2a35-4135-8064-9fb280782ad0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479296245 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.1479296245 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.1241042284
Short name	T1104
Test name
Test status
Simulation time	76069349 ps
CPU time	1.02 seconds
Started	Jun 04 12:46:08 PM PDT 24
Finished	Jun 04 12:46:12 PM PDT 24
Peak memory	215840 kb
Host	smart-2d3a6f27-c48f-43d1-ae5c-4552c3e5beae
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241042284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1241042284 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_intr_test.2585125620
Short name	T1246
Test name
Test status
Simulation time	22023363 ps
CPU time	0.81 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:12 PM PDT 24
Peak memory	215676 kb
Host	smart-a0de90e7-0ad8-4b0f-a681-79e67623ee5b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585125620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.2585125620 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2139293285
Short name	T1201
Test name
Test status
Simulation time	119370793 ps
CPU time	2.42 seconds
Started	Jun 04 12:46:10 PM PDT 24
Finished	Jun 04 12:46:15 PM PDT 24
Peak memory	215816 kb
Host	smart-6f4f4fc7-d27c-483a-9033-8739f3000c44
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139293285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs r_outstanding.2139293285 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.336833196
Short name	T93
Test name
Test status
Simulation time	54099061 ps
CPU time	1.72 seconds
Started	Jun 04 12:46:19 PM PDT 24
Finished	Jun 04 12:46:22 PM PDT 24
Peak memory	218636 kb
Host	smart-36d922fa-8d9a-40e0-89c7-c6d28ea36cc6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336833196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac _shadow_reg_errors_with_csr_rw.336833196 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.1220051674
Short name	T1216
Test name
Test status
Simulation time	76110446 ps
CPU time	2.04 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:13 PM PDT 24
Peak memory	215972 kb
Host	smart-f71c281d-c489-4cad-984b-2e5aff5b0727
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220051674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1220051674 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3808837115
Short name	T1207
Test name
Test status
Simulation time	87422212 ps
CPU time	2.35 seconds
Started	Jun 04 12:46:18 PM PDT 24
Finished	Jun 04 12:46:22 PM PDT 24
Peak memory	221000 kb
Host	smart-bb8c379f-cc7b-4f77-8338-1d6be673ae06
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808837115 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.3808837115 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.1048139698
Short name	T1133
Test name
Test status
Simulation time	83777459 ps
CPU time	1.02 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:12 PM PDT 24
Peak memory	215704 kb
Host	smart-c78bfce9-7bf7-427d-94da-21f2f2062894
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048139698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.1048139698 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_intr_test.100132543
Short name	T1157
Test name
Test status
Simulation time	15244030 ps
CPU time	0.8 seconds
Started	Jun 04 12:46:12 PM PDT 24
Finished	Jun 04 12:46:15 PM PDT 24
Peak memory	215760 kb
Host	smart-4a668955-d9f0-42d9-8c0d-c7b2821749bb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100132543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.100132543 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2553470827
Short name	T1086
Test name
Test status
Simulation time	84357992 ps
CPU time	1.38 seconds
Started	Jun 04 12:46:15 PM PDT 24
Finished	Jun 04 12:46:17 PM PDT 24
Peak memory	216004 kb
Host	smart-37e15c48-edff-44d0-a416-5be6dbe87d74
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553470827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs r_outstanding.2553470827 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.4104425517
Short name	T87
Test name
Test status
Simulation time	309029572 ps
CPU time	1.94 seconds
Started	Jun 04 12:46:10 PM PDT 24
Finished	Jun 04 12:46:14 PM PDT 24
Peak memory	218192 kb
Host	smart-3403c860-d22f-4aff-b019-8c9e41f31608
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104425517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma c_shadow_reg_errors_with_csr_rw.4104425517 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.2544021936
Short name	T1136
Test name
Test status
Simulation time	83222174 ps
CPU time	2.77 seconds
Started	Jun 04 12:46:11 PM PDT 24
Finished	Jun 04 12:46:16 PM PDT 24
Peak memory	216008 kb
Host	smart-e6cdcc5b-970e-4eb5-ad9c-3b880e6ed712
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544021936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.2544021936 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3620892357
Short name	T176
Test name
Test status
Simulation time	431924864 ps
CPU time	4.94 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:16 PM PDT 24
Peak memory	216072 kb
Host	smart-1afb7d1e-2d9d-45c6-8118-398494742b47
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620892357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3620 892357 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1823189795
Short name	T1204
Test name
Test status
Simulation time	45271764 ps
CPU time	1.73 seconds
Started	Jun 04 12:46:16 PM PDT 24
Finished	Jun 04 12:46:19 PM PDT 24
Peak memory	221748 kb
Host	smart-5f15d393-50cd-4fdf-b1b6-cb52d97cb635
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823189795 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.1823189795 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.2292278494
Short name	T1232
Test name
Test status
Simulation time	20695407 ps
CPU time	1 seconds
Started	Jun 04 12:46:17 PM PDT 24
Finished	Jun 04 12:46:19 PM PDT 24
Peak memory	215740 kb
Host	smart-53b330ac-b2b7-47f6-9438-6f1036a964c1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292278494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.2292278494 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_intr_test.4078386225
Short name	T1108
Test name
Test status
Simulation time	18286892 ps
CPU time	0.8 seconds
Started	Jun 04 12:46:20 PM PDT 24
Finished	Jun 04 12:46:22 PM PDT 24
Peak memory	215704 kb
Host	smart-5f204992-646b-4603-b330-791f436d0f4c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078386225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.4078386225 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1023360009
Short name	T1119
Test name
Test status
Simulation time	567392385 ps
CPU time	2.15 seconds
Started	Jun 04 12:46:18 PM PDT 24
Finished	Jun 04 12:46:22 PM PDT 24
Peak memory	215980 kb
Host	smart-999b113b-8fbb-4ae2-8fdb-289e1565c336
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023360009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs r_outstanding.1023360009 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1574566267
Short name	T1211
Test name
Test status
Simulation time	46374262 ps
CPU time	1.13 seconds
Started	Jun 04 12:46:17 PM PDT 24
Finished	Jun 04 12:46:20 PM PDT 24
Peak memory	216420 kb
Host	smart-67527988-6032-4302-b4cb-f275e0dc8aa5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574566267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg _errors.1574566267 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1558784141
Short name	T1229
Test name
Test status
Simulation time	478338637 ps
CPU time	2.78 seconds
Started	Jun 04 12:46:18 PM PDT 24
Finished	Jun 04 12:46:23 PM PDT 24
Peak memory	218788 kb
Host	smart-fd976847-b328-4ee4-bb41-8eabe40984ae
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558784141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma c_shadow_reg_errors_with_csr_rw.1558784141 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.3544895997
Short name	T1127
Test name
Test status
Simulation time	217433053 ps
CPU time	2.34 seconds
Started	Jun 04 12:46:23 PM PDT 24
Finished	Jun 04 12:46:26 PM PDT 24
Peak memory	216052 kb
Host	smart-aa219f71-8ecb-471e-8717-3c35611c83fd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544895997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3544895997 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1119501207
Short name	T149
Test name
Test status
Simulation time	303949269 ps
CPU time	2.67 seconds
Started	Jun 04 12:46:16 PM PDT 24
Finished	Jun 04 12:46:20 PM PDT 24
Peak memory	220828 kb
Host	smart-63656651-12ca-4eea-b3e3-b2d5b3e1e75b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119501207 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.1119501207 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.4111276865
Short name	T1199
Test name
Test status
Simulation time	41997980 ps
CPU time	1.06 seconds
Started	Jun 04 12:46:17 PM PDT 24
Finished	Jun 04 12:46:19 PM PDT 24
Peak memory	215516 kb
Host	smart-dfd42eb6-9884-4146-8ae1-f00e2a1aebd8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111276865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.4111276865 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_intr_test.423045846
Short name	T1161
Test name
Test status
Simulation time	14346942 ps
CPU time	0.82 seconds
Started	Jun 04 12:46:18 PM PDT 24
Finished	Jun 04 12:46:20 PM PDT 24
Peak memory	215740 kb
Host	smart-2dca7da9-c6e7-40ba-812b-33ed79339424
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423045846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.423045846 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.1184100135
Short name	T1128
Test name
Test status
Simulation time	116820710 ps
CPU time	2.2 seconds
Started	Jun 04 12:46:17 PM PDT 24
Finished	Jun 04 12:46:20 PM PDT 24
Peak memory	216040 kb
Host	smart-89688a67-ab00-4ccf-8ee5-0da03e0aec37
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184100135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs r_outstanding.1184100135 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.1038473506
Short name	T1172
Test name
Test status
Simulation time	58552531 ps
CPU time	1.71 seconds
Started	Jun 04 12:46:17 PM PDT 24
Finished	Jun 04 12:46:21 PM PDT 24
Peak memory	218692 kb
Host	smart-574c23e6-dd1c-4c28-bd5e-031c3e63d5f6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038473506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma c_shadow_reg_errors_with_csr_rw.1038473506 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.3205161046
Short name	T1110
Test name
Test status
Simulation time	90245455 ps
CPU time	2.62 seconds
Started	Jun 04 12:46:17 PM PDT 24
Finished	Jun 04 12:46:20 PM PDT 24
Peak memory	215920 kb
Host	smart-a6eaedc7-a27b-4648-812c-0cd27d033332
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205161046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.3205161046 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.1440834644
Short name	T1162
Test name
Test status
Simulation time	91416188 ps
CPU time	1.8 seconds
Started	Jun 04 12:46:16 PM PDT 24
Finished	Jun 04 12:46:19 PM PDT 24
Peak memory	220688 kb
Host	smart-30ba9e57-cb96-443d-ab92-420a4a6175f7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440834644 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.1440834644 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.2296107803
Short name	T1238
Test name
Test status
Simulation time	27164065 ps
CPU time	1.1 seconds
Started	Jun 04 12:46:17 PM PDT 24
Finished	Jun 04 12:46:19 PM PDT 24
Peak memory	215504 kb
Host	smart-8f59184a-751a-4083-88db-d6ef9b348b76
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296107803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.2296107803 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_intr_test.1343928752
Short name	T1240
Test name
Test status
Simulation time	17339644 ps
CPU time	0.8 seconds
Started	Jun 04 12:46:20 PM PDT 24
Finished	Jun 04 12:46:23 PM PDT 24
Peak memory	215752 kb
Host	smart-13bbe8cc-0755-4396-b34d-fe97c12c8775
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343928752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.1343928752 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.697684409
Short name	T1186
Test name
Test status
Simulation time	123362219 ps
CPU time	2.15 seconds
Started	Jun 04 12:46:20 PM PDT 24
Finished	Jun 04 12:46:24 PM PDT 24
Peak memory	216024 kb
Host	smart-c8b40996-2a61-481b-8b73-431e5534f54c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697684409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr _outstanding.697684409 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2813312300
Short name	T97
Test name
Test status
Simulation time	125689656 ps
CPU time	1.11 seconds
Started	Jun 04 12:46:18 PM PDT 24
Finished	Jun 04 12:46:21 PM PDT 24
Peak memory	216264 kb
Host	smart-92c83ef1-40bc-49ab-858e-2f4b866d15c4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813312300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg _errors.2813312300 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.4069568767
Short name	T1205
Test name
Test status
Simulation time	564374991 ps
CPU time	2.78 seconds
Started	Jun 04 12:46:17 PM PDT 24
Finished	Jun 04 12:46:21 PM PDT 24
Peak memory	218724 kb
Host	smart-b0b4a3af-e7e1-4904-b5de-05e8054bbff1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069568767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma c_shadow_reg_errors_with_csr_rw.4069568767 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.1589190702
Short name	T1189
Test name
Test status
Simulation time	36315530 ps
CPU time	2.25 seconds
Started	Jun 04 12:46:23 PM PDT 24
Finished	Jun 04 12:46:26 PM PDT 24
Peak memory	215992 kb
Host	smart-7958c033-f5d9-4bb5-8db9-f5b2cbe6215f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589190702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.1589190702 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3107025929
Short name	T1228
Test name
Test status
Simulation time	949082734 ps
CPU time	5.05 seconds
Started	Jun 04 12:46:16 PM PDT 24
Finished	Jun 04 12:46:22 PM PDT 24
Peak memory	216000 kb
Host	smart-6706bc50-41a3-45cc-b4c8-6377e40f3d20
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107025929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3107 025929 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2150473514
Short name	T1223
Test name
Test status
Simulation time	69470109 ps
CPU time	2.32 seconds
Started	Jun 04 12:46:17 PM PDT 24
Finished	Jun 04 12:46:20 PM PDT 24
Peak memory	221528 kb
Host	smart-68428a47-1218-4e8a-954e-a5d31e4e85c9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150473514 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.2150473514 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.1205219323
Short name	T1088
Test name
Test status
Simulation time	14626046 ps
CPU time	0.95 seconds
Started	Jun 04 12:46:17 PM PDT 24
Finished	Jun 04 12:46:20 PM PDT 24
Peak memory	215744 kb
Host	smart-2f935f63-4fe4-495f-959c-77c1e89cd511
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205219323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.1205219323 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_intr_test.2810884273
Short name	T1115
Test name
Test status
Simulation time	15431621 ps
CPU time	0.79 seconds
Started	Jun 04 12:46:21 PM PDT 24
Finished	Jun 04 12:46:23 PM PDT 24
Peak memory	215748 kb
Host	smart-5d8c4740-dd81-4e82-9676-1a3b1258d5f3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810884273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.2810884273 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1418220214
Short name	T1193
Test name
Test status
Simulation time	28288112 ps
CPU time	1.5 seconds
Started	Jun 04 12:46:21 PM PDT 24
Finished	Jun 04 12:46:24 PM PDT 24
Peak memory	216008 kb
Host	smart-f7e6e4ac-a2fa-49c6-a620-2596f81c37fe
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418220214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs r_outstanding.1418220214 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2595405968
Short name	T1151
Test name
Test status
Simulation time	62617364 ps
CPU time	1.75 seconds
Started	Jun 04 12:46:18 PM PDT 24
Finished	Jun 04 12:46:21 PM PDT 24
Peak memory	216324 kb
Host	smart-c18fc9dd-279e-4316-820b-22a50de43857
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595405968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma c_shadow_reg_errors_with_csr_rw.2595405968 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.612831465
Short name	T1169
Test name
Test status
Simulation time	173032007 ps
CPU time	1.64 seconds
Started	Jun 04 12:46:21 PM PDT 24
Finished	Jun 04 12:46:24 PM PDT 24
Peak memory	216080 kb
Host	smart-b88a3d82-fa1a-4c20-b7ec-e000c9a02038
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612831465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.612831465 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.78480867
Short name	T1234
Test name
Test status
Simulation time	130194370 ps
CPU time	2.82 seconds
Started	Jun 04 12:46:16 PM PDT 24
Finished	Jun 04 12:46:19 PM PDT 24
Peak memory	215936 kb
Host	smart-8e05f444-1b6c-43bb-a9a9-7a3a3033b4b5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78480867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.784808 67 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.243462993
Short name	T1145
Test name
Test status
Simulation time	142082691 ps
CPU time	4.14 seconds
Started	Jun 04 12:45:50 PM PDT 24
Finished	Jun 04 12:45:55 PM PDT 24
Peak memory	215932 kb
Host	smart-1f5f9935-ece0-48e3-86b0-657f81881fc4
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243462993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.24346299 3 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.2676599749
Short name	T1098
Test name
Test status
Simulation time	1127714002 ps
CPU time	15.51 seconds
Started	Jun 04 12:45:50 PM PDT 24
Finished	Jun 04 12:46:07 PM PDT 24
Peak memory	215944 kb
Host	smart-dc327df0-7909-49d0-afe3-76df3e834166
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676599749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.2676599 749 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.326724990
Short name	T1121
Test name
Test status
Simulation time	60318819 ps
CPU time	1.24 seconds
Started	Jun 04 12:45:50 PM PDT 24
Finished	Jun 04 12:45:53 PM PDT 24
Peak memory	215928 kb
Host	smart-2f61aa78-4227-426f-af64-cb76ab02ec24
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326724990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.32672499 0 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.276379945
Short name	T1187
Test name
Test status
Simulation time	68396654 ps
CPU time	1.55 seconds
Started	Jun 04 12:45:48 PM PDT 24
Finished	Jun 04 12:45:52 PM PDT 24
Peak memory	217944 kb
Host	smart-df7d27eb-8001-4276-ade2-172e0b32b6a4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276379945 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.276379945 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.748167215
Short name	T1183
Test name
Test status
Simulation time	17567303 ps
CPU time	1.18 seconds
Started	Jun 04 12:45:47 PM PDT 24
Finished	Jun 04 12:45:49 PM PDT 24
Peak memory	215880 kb
Host	smart-de5041c3-5dca-4782-9293-585aeb1e70b8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748167215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.748167215 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_intr_test.3191231189
Short name	T1184
Test name
Test status
Simulation time	105183385 ps
CPU time	0.77 seconds
Started	Jun 04 12:45:49 PM PDT 24
Finished	Jun 04 12:45:51 PM PDT 24
Peak memory	215732 kb
Host	smart-1e5268ab-ba10-4110-9b77-a474318c1c2e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191231189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3191231189 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.3267174319
Short name	T142
Test name
Test status
Simulation time	51964470 ps
CPU time	1.16 seconds
Started	Jun 04 12:45:50 PM PDT 24
Finished	Jun 04 12:45:52 PM PDT 24
Peak memory	216012 kb
Host	smart-a2e7e3d3-8a8b-4b03-ba28-68eae13b0d2a
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267174319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia l_access.3267174319 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.4100442700
Short name	T1144
Test name
Test status
Simulation time	30292088 ps
CPU time	0.72 seconds
Started	Jun 04 12:45:47 PM PDT 24
Finished	Jun 04 12:45:48 PM PDT 24
Peak memory	215888 kb
Host	smart-0cf6755f-cf33-400a-890e-da3c2c48d286
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100442700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.4100442700 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2695107700
Short name	T1233
Test name
Test status
Simulation time	347954151 ps
CPU time	1.66 seconds
Started	Jun 04 12:45:49 PM PDT 24
Finished	Jun 04 12:45:52 PM PDT 24
Peak memory	215912 kb
Host	smart-bfe68c25-b6ca-4e5d-a6f6-157253193064
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695107700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr _outstanding.2695107700 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2661201102
Short name	T90
Test name
Test status
Simulation time	84449731 ps
CPU time	1.27 seconds
Started	Jun 04 12:45:49 PM PDT 24
Finished	Jun 04 12:45:52 PM PDT 24
Peak memory	216580 kb
Host	smart-6e83a2f7-7fb7-45a4-afb0-8cdb461e9c20
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661201102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_ errors.2661201102 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1458854097
Short name	T1166
Test name
Test status
Simulation time	57499446 ps
CPU time	1.98 seconds
Started	Jun 04 12:45:50 PM PDT 24
Finished	Jun 04 12:45:54 PM PDT 24
Peak memory	219576 kb
Host	smart-7e7218a7-6e70-49cb-b65e-57c0d26dbc25
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458854097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac _shadow_reg_errors_with_csr_rw.1458854097 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.691938963
Short name	T1125
Test name
Test status
Simulation time	184316859 ps
CPU time	2.74 seconds
Started	Jun 04 12:45:49 PM PDT 24
Finished	Jun 04 12:45:54 PM PDT 24
Peak memory	216132 kb
Host	smart-cd8a8942-a139-483a-8c89-0c56cc55efbc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691938963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.691938963 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3837562065
Short name	T1130
Test name
Test status
Simulation time	479714695 ps
CPU time	3.05 seconds
Started	Jun 04 12:45:48 PM PDT 24
Finished	Jun 04 12:45:52 PM PDT 24
Peak memory	215856 kb
Host	smart-56a5ee56-d266-4ae8-a895-20620c8b978a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837562065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.38375 62065 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.kmac_intr_test.556434481
Short name	T1188
Test name
Test status
Simulation time	21684835 ps
CPU time	0.86 seconds
Started	Jun 04 12:46:17 PM PDT 24
Finished	Jun 04 12:46:20 PM PDT 24
Peak memory	215556 kb
Host	smart-5ab2d1d6-1a0a-432a-b240-b70872a64fc7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556434481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.556434481 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.kmac_intr_test.3711558510
Short name	T162
Test name
Test status
Simulation time	16892782 ps
CPU time	0.83 seconds
Started	Jun 04 12:46:20 PM PDT 24
Finished	Jun 04 12:46:22 PM PDT 24
Peak memory	215596 kb
Host	smart-8fc3641a-759a-4387-9512-b62cb9e1ce8d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711558510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3711558510 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.kmac_intr_test.838973907
Short name	T1142
Test name
Test status
Simulation time	22124181 ps
CPU time	0.73 seconds
Started	Jun 04 12:46:23 PM PDT 24
Finished	Jun 04 12:46:25 PM PDT 24
Peak memory	215684 kb
Host	smart-2226f4a4-3abd-4eab-a390-98913bc452d0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838973907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.838973907 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.kmac_intr_test.3161366923
Short name	T1243
Test name
Test status
Simulation time	84228471 ps
CPU time	0.77 seconds
Started	Jun 04 12:46:21 PM PDT 24
Finished	Jun 04 12:46:23 PM PDT 24
Peak memory	215692 kb
Host	smart-261a0a38-6907-4c9f-b0de-3aafc2a14aaa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161366923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.3161366923 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.kmac_intr_test.2166161280
Short name	T1230
Test name
Test status
Simulation time	35410028 ps
CPU time	0.76 seconds
Started	Jun 04 12:46:20 PM PDT 24
Finished	Jun 04 12:46:22 PM PDT 24
Peak memory	215704 kb
Host	smart-975b7157-805c-4812-82ed-14a4c94ec474
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166161280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2166161280 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.kmac_intr_test.1990121867
Short name	T1222
Test name
Test status
Simulation time	12788660 ps
CPU time	0.82 seconds
Started	Jun 04 12:46:20 PM PDT 24
Finished	Jun 04 12:46:22 PM PDT 24
Peak memory	215648 kb
Host	smart-b3410238-b215-49b2-b725-fed54ddf02a6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990121867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.1990121867 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.kmac_intr_test.1489006572
Short name	T129
Test name
Test status
Simulation time	34645743 ps
CPU time	0.77 seconds
Started	Jun 04 12:46:18 PM PDT 24
Finished	Jun 04 12:46:20 PM PDT 24
Peak memory	215596 kb
Host	smart-09c7340a-0206-48da-b62f-789effbf156e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489006572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.1489006572 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.kmac_intr_test.3250065125
Short name	T1109
Test name
Test status
Simulation time	12571151 ps
CPU time	0.82 seconds
Started	Jun 04 12:46:20 PM PDT 24
Finished	Jun 04 12:46:22 PM PDT 24
Peak memory	215696 kb
Host	smart-12fdad31-ae29-4b88-b98e-b17dfea65982
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250065125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.3250065125 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.kmac_intr_test.4109456301
Short name	T1132
Test name
Test status
Simulation time	60118732 ps
CPU time	0.73 seconds
Started	Jun 04 12:46:24 PM PDT 24
Finished	Jun 04 12:46:26 PM PDT 24
Peak memory	215676 kb
Host	smart-65cd7d94-dd79-4460-8b80-04762ffc12dc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109456301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.4109456301 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.2323779975
Short name	T1247
Test name
Test status
Simulation time	1557949783 ps
CPU time	9.7 seconds
Started	Jun 04 12:45:48 PM PDT 24
Finished	Jun 04 12:45:59 PM PDT 24
Peak memory	215960 kb
Host	smart-c51fbb13-ed04-47e5-814f-36b302f0bc66
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323779975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.2323779 975 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.4029803338
Short name	T1241
Test name
Test status
Simulation time	297966540 ps
CPU time	8.29 seconds
Started	Jun 04 12:45:48 PM PDT 24
Finished	Jun 04 12:45:57 PM PDT 24
Peak memory	216040 kb
Host	smart-63ca43d9-e320-4677-b358-d44e2239cc09
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029803338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.4029803 338 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.4147587210
Short name	T1140
Test name
Test status
Simulation time	32075462 ps
CPU time	1.12 seconds
Started	Jun 04 12:45:49 PM PDT 24
Finished	Jun 04 12:45:52 PM PDT 24
Peak memory	216024 kb
Host	smart-7dc3e5b1-4b97-4d00-8063-4da93b35028b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147587210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.4147587 210 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3899858692
Short name	T150
Test name
Test status
Simulation time	93939982 ps
CPU time	1.62 seconds
Started	Jun 04 12:45:59 PM PDT 24
Finished	Jun 04 12:46:03 PM PDT 24
Peak memory	217132 kb
Host	smart-da08158b-ad8d-46eb-9879-2e6fdda7a108
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899858692 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.3899858692 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.1226744978
Short name	T1139
Test name
Test status
Simulation time	123533397 ps
CPU time	1.17 seconds
Started	Jun 04 12:45:57 PM PDT 24
Finished	Jun 04 12:45:59 PM PDT 24
Peak memory	215892 kb
Host	smart-b9c101d3-693b-42c6-a13b-20a26b913927
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226744978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.1226744978 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_intr_test.879391131
Short name	T1249
Test name
Test status
Simulation time	27285342 ps
CPU time	0.87 seconds
Started	Jun 04 12:45:52 PM PDT 24
Finished	Jun 04 12:45:54 PM PDT 24
Peak memory	215744 kb
Host	smart-6097ac13-ad19-40f0-80e1-af4db2197bdc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879391131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.879391131 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.358246391
Short name	T138
Test name
Test status
Simulation time	28842096 ps
CPU time	1.26 seconds
Started	Jun 04 12:45:57 PM PDT 24
Finished	Jun 04 12:46:00 PM PDT 24
Peak memory	215936 kb
Host	smart-af284b7a-db16-471c-a23f-19b60b3ae164
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358246391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial _access.358246391 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.3116410372
Short name	T1089
Test name
Test status
Simulation time	26875755 ps
CPU time	0.74 seconds
Started	Jun 04 12:45:57 PM PDT 24
Finished	Jun 04 12:45:59 PM PDT 24
Peak memory	215756 kb
Host	smart-9b9192e2-02aa-4f8d-a682-92dd289c4960
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116410372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3116410372 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1799747966
Short name	T1131
Test name
Test status
Simulation time	454166480 ps
CPU time	2.62 seconds
Started	Jun 04 12:45:56 PM PDT 24
Finished	Jun 04 12:46:00 PM PDT 24
Peak memory	216080 kb
Host	smart-16a56980-d08d-4d8c-bbdd-af0df9bc4709
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799747966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr _outstanding.1799747966 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.882697343
Short name	T91
Test name
Test status
Simulation time	20137423 ps
CPU time	1.04 seconds
Started	Jun 04 12:45:57 PM PDT 24
Finished	Jun 04 12:46:00 PM PDT 24
Peak memory	216004 kb
Host	smart-5939b38f-ac25-4d93-abec-7b6c8063068e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882697343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_e rrors.882697343 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1843536950
Short name	T1253
Test name
Test status
Simulation time	59427788 ps
CPU time	1.93 seconds
Started	Jun 04 12:45:50 PM PDT 24
Finished	Jun 04 12:45:53 PM PDT 24
Peak memory	216220 kb
Host	smart-38ce5f02-20f0-4e1f-8742-c3ec2b88c061
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843536950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac _shadow_reg_errors_with_csr_rw.1843536950 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.3045968669
Short name	T1180
Test name
Test status
Simulation time	59922079 ps
CPU time	1.84 seconds
Started	Jun 04 12:45:50 PM PDT 24
Finished	Jun 04 12:45:53 PM PDT 24
Peak memory	216028 kb
Host	smart-2e1f04f1-1a0f-4b00-b32b-2713bd16c342
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045968669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.3045968669 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3837752098
Short name	T175
Test name
Test status
Simulation time	246775316 ps
CPU time	2.91 seconds
Started	Jun 04 12:45:49 PM PDT 24
Finished	Jun 04 12:45:53 PM PDT 24
Peak memory	215972 kb
Host	smart-522d32d8-a2c8-4b57-9e9b-c10f378a023f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837752098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.38377 52098 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.kmac_intr_test.2638726635
Short name	T1092
Test name
Test status
Simulation time	24218380 ps
CPU time	0.81 seconds
Started	Jun 04 12:46:24 PM PDT 24
Finished	Jun 04 12:46:26 PM PDT 24
Peak memory	215624 kb
Host	smart-ceee5664-5c7c-4536-b80e-cf4add8cb2aa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638726635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2638726635 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.kmac_intr_test.2993322981
Short name	T1126
Test name
Test status
Simulation time	81125304 ps
CPU time	0.8 seconds
Started	Jun 04 12:46:21 PM PDT 24
Finished	Jun 04 12:46:23 PM PDT 24
Peak memory	215688 kb
Host	smart-c89d8e5b-62c8-4159-9588-a0500358c455
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993322981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.2993322981 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.kmac_intr_test.387010484
Short name	T1101
Test name
Test status
Simulation time	13293530 ps
CPU time	0.77 seconds
Started	Jun 04 12:46:21 PM PDT 24
Finished	Jun 04 12:46:23 PM PDT 24
Peak memory	215680 kb
Host	smart-0e19bbc3-24cc-446a-b72f-5b2d44c4d4b8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387010484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.387010484 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.kmac_intr_test.2867952563
Short name	T1143
Test name
Test status
Simulation time	15547624 ps
CPU time	0.79 seconds
Started	Jun 04 12:46:21 PM PDT 24
Finished	Jun 04 12:46:23 PM PDT 24
Peak memory	215688 kb
Host	smart-aceb97db-3a29-481c-b668-8f921e0f2ca7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867952563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2867952563 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.kmac_intr_test.3794244676
Short name	T1202
Test name
Test status
Simulation time	45668361 ps
CPU time	0.81 seconds
Started	Jun 04 12:46:21 PM PDT 24
Finished	Jun 04 12:46:23 PM PDT 24
Peak memory	215716 kb
Host	smart-1ec4c401-5bf5-4ea4-8160-d446877dad63
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794244676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3794244676 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.kmac_intr_test.1545452444
Short name	T130
Test name
Test status
Simulation time	13094914 ps
CPU time	0.8 seconds
Started	Jun 04 12:46:17 PM PDT 24
Finished	Jun 04 12:46:20 PM PDT 24
Peak memory	215692 kb
Host	smart-74002b6d-5417-4cc6-99c2-d617d562c6b9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545452444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1545452444 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.kmac_intr_test.3830555564
Short name	T1218
Test name
Test status
Simulation time	48839730 ps
CPU time	0.77 seconds
Started	Jun 04 12:46:17 PM PDT 24
Finished	Jun 04 12:46:29 PM PDT 24
Peak memory	215892 kb
Host	smart-2f8e6be0-1de9-404d-86a2-e4f8da093c94
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830555564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.3830555564 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.kmac_intr_test.893765113
Short name	T1149
Test name
Test status
Simulation time	206077138 ps
CPU time	0.81 seconds
Started	Jun 04 12:46:22 PM PDT 24
Finished	Jun 04 12:46:24 PM PDT 24
Peak memory	215696 kb
Host	smart-6f7d319f-0c1a-48de-8d8d-333fa4aad03f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893765113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.893765113 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.kmac_intr_test.2934016016
Short name	T1210
Test name
Test status
Simulation time	49084929 ps
CPU time	0.77 seconds
Started	Jun 04 12:46:26 PM PDT 24
Finished	Jun 04 12:46:29 PM PDT 24
Peak memory	215712 kb
Host	smart-59f73e04-584b-476f-a326-1a134584d880
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934016016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2934016016 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.kmac_intr_test.1905675743
Short name	T1192
Test name
Test status
Simulation time	19171382 ps
CPU time	0.78 seconds
Started	Jun 04 12:46:22 PM PDT 24
Finished	Jun 04 12:46:24 PM PDT 24
Peak memory	215624 kb
Host	smart-502c834c-b42b-4d13-8466-2d675605f06b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905675743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1905675743 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3950458902
Short name	T1175
Test name
Test status
Simulation time	204827983 ps
CPU time	4.86 seconds
Started	Jun 04 12:45:59 PM PDT 24
Finished	Jun 04 12:46:05 PM PDT 24
Peak memory	215884 kb
Host	smart-9d787af7-415c-4cba-9d06-9ec31f8b1765
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950458902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3950458 902 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1656838572
Short name	T1150
Test name
Test status
Simulation time	1509328970 ps
CPU time	20.9 seconds
Started	Jun 04 12:45:56 PM PDT 24
Finished	Jun 04 12:46:18 PM PDT 24
Peak memory	216052 kb
Host	smart-60154805-193a-415c-b97b-3ffe41533330
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656838572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.1656838 572 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.2708437724
Short name	T1219
Test name
Test status
Simulation time	41199479 ps
CPU time	1.13 seconds
Started	Jun 04 12:45:59 PM PDT 24
Finished	Jun 04 12:46:02 PM PDT 24
Peak memory	215868 kb
Host	smart-b21bd731-d5de-43cc-bb94-a38ae435af6f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708437724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.2708437 724 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1671237586
Short name	T1141
Test name
Test status
Simulation time	25274338 ps
CPU time	1.65 seconds
Started	Jun 04 12:45:59 PM PDT 24
Finished	Jun 04 12:46:02 PM PDT 24
Peak memory	220336 kb
Host	smart-f543fbaf-5351-4b27-b2a8-e4f007e26a57
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671237586 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.1671237586 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.1632781649
Short name	T1174
Test name
Test status
Simulation time	27943234 ps
CPU time	1.17 seconds
Started	Jun 04 12:45:56 PM PDT 24
Finished	Jun 04 12:45:59 PM PDT 24
Peak memory	216088 kb
Host	smart-76e981a1-7b70-4993-9720-d234abb8574b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632781649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.1632781649 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_intr_test.2834784484
Short name	T1190
Test name
Test status
Simulation time	15988868 ps
CPU time	0.81 seconds
Started	Jun 04 12:45:57 PM PDT 24
Finished	Jun 04 12:46:00 PM PDT 24
Peak memory	215836 kb
Host	smart-1ab510a2-f1cd-456b-b2bd-6f4816763fa7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834784484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.2834784484 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.1437371198
Short name	T140
Test name
Test status
Simulation time	59367794 ps
CPU time	1.33 seconds
Started	Jun 04 12:45:58 PM PDT 24
Finished	Jun 04 12:46:01 PM PDT 24
Peak memory	216084 kb
Host	smart-b6a47c53-c5cd-45b4-85a5-0644ab54030f
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437371198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia l_access.1437371198 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.1775684708
Short name	T1087
Test name
Test status
Simulation time	13705930 ps
CPU time	0.76 seconds
Started	Jun 04 12:45:59 PM PDT 24
Finished	Jun 04 12:46:02 PM PDT 24
Peak memory	215740 kb
Host	smart-ee5f6f84-e506-4b45-9f18-a47654c1aba7
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775684708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.1775684708 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2009460180
Short name	T1182
Test name
Test status
Simulation time	47539176 ps
CPU time	1.54 seconds
Started	Jun 04 12:45:57 PM PDT 24
Finished	Jun 04 12:46:00 PM PDT 24
Peak memory	215980 kb
Host	smart-1b28683f-739d-4edb-915c-db518ed12ae2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009460180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr _outstanding.2009460180 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2412184292
Short name	T1124
Test name
Test status
Simulation time	99236582 ps
CPU time	1.61 seconds
Started	Jun 04 12:45:59 PM PDT 24
Finished	Jun 04 12:46:02 PM PDT 24
Peak memory	216640 kb
Host	smart-5b1468e4-135a-468b-86c1-713bd0890a99
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412184292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_ errors.2412184292 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2679550325
Short name	T85
Test name
Test status
Simulation time	56983869 ps
CPU time	1.85 seconds
Started	Jun 04 12:45:59 PM PDT 24
Finished	Jun 04 12:46:02 PM PDT 24
Peak memory	218632 kb
Host	smart-69e22f30-6e0c-4bbe-800c-50729c31d6ea
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679550325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac _shadow_reg_errors_with_csr_rw.2679550325 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.1712354430
Short name	T1146
Test name
Test status
Simulation time	78552044 ps
CPU time	2.64 seconds
Started	Jun 04 12:45:57 PM PDT 24
Finished	Jun 04 12:46:01 PM PDT 24
Peak memory	216052 kb
Host	smart-290c1e22-b8ab-4352-aeda-3803798a6c3d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712354430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.1712354430 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.147068689
Short name	T1176
Test name
Test status
Simulation time	400775392 ps
CPU time	2.94 seconds
Started	Jun 04 12:45:58 PM PDT 24
Finished	Jun 04 12:46:02 PM PDT 24
Peak memory	216008 kb
Host	smart-5ac0d27f-b9b8-4b2e-b717-6f21cdbd62c8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147068689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.147068 689 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.kmac_intr_test.3481690790
Short name	T1245
Test name
Test status
Simulation time	15048566 ps
CPU time	0.75 seconds
Started	Jun 04 12:46:21 PM PDT 24
Finished	Jun 04 12:46:23 PM PDT 24
Peak memory	215680 kb
Host	smart-d5c3a836-64e6-4aee-bd45-76ac25ef7484
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481690790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.3481690790 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.kmac_intr_test.161499222
Short name	T1096
Test name
Test status
Simulation time	15573103 ps
CPU time	0.78 seconds
Started	Jun 04 12:46:26 PM PDT 24
Finished	Jun 04 12:46:29 PM PDT 24
Peak memory	215664 kb
Host	smart-9f91f1f1-8a5b-46c0-af0f-23e51165835b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161499222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.161499222 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.kmac_intr_test.811836737
Short name	T161
Test name
Test status
Simulation time	24124812 ps
CPU time	0.8 seconds
Started	Jun 04 12:46:18 PM PDT 24
Finished	Jun 04 12:46:20 PM PDT 24
Peak memory	215704 kb
Host	smart-ac1cc2ad-dc42-4f1f-82c9-db24cc8b5b78
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811836737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.811836737 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.kmac_intr_test.91100165
Short name	T1191
Test name
Test status
Simulation time	14401763 ps
CPU time	0.78 seconds
Started	Jun 04 12:46:16 PM PDT 24
Finished	Jun 04 12:46:18 PM PDT 24
Peak memory	215672 kb
Host	smart-ef1032d2-ab00-49d5-9e2a-268f071647d6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91100165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.91100165 +enable_mas king=1 +sw_key_masked=0
Directory	/workspace/43.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.kmac_intr_test.3407851947
Short name	T1231
Test name
Test status
Simulation time	40989799 ps
CPU time	0.85 seconds
Started	Jun 04 12:46:19 PM PDT 24
Finished	Jun 04 12:46:22 PM PDT 24
Peak memory	215840 kb
Host	smart-00c9120e-f190-4171-bed4-1ced7254b74e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407851947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3407851947 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.kmac_intr_test.979549507
Short name	T1099
Test name
Test status
Simulation time	36525208 ps
CPU time	0.8 seconds
Started	Jun 04 12:46:18 PM PDT 24
Finished	Jun 04 12:46:20 PM PDT 24
Peak memory	215760 kb
Host	smart-0960968a-fca0-4b83-bc29-780d77fe73d1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979549507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.979549507 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.kmac_intr_test.2191934996
Short name	T163
Test name
Test status
Simulation time	43565175 ps
CPU time	0.85 seconds
Started	Jun 04 12:46:18 PM PDT 24
Finished	Jun 04 12:46:21 PM PDT 24
Peak memory	215932 kb
Host	smart-a412ee61-957c-4230-b35f-82adb329ed06
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191934996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2191934996 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.kmac_intr_test.299882908
Short name	T1220
Test name
Test status
Simulation time	60208121 ps
CPU time	0.78 seconds
Started	Jun 04 12:46:26 PM PDT 24
Finished	Jun 04 12:46:29 PM PDT 24
Peak memory	215664 kb
Host	smart-3df73f85-2148-402e-a6a4-fb868a87f79b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299882908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.299882908 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.kmac_intr_test.2529130624
Short name	T1105
Test name
Test status
Simulation time	30916160 ps
CPU time	0.85 seconds
Started	Jun 04 12:46:17 PM PDT 24
Finished	Jun 04 12:46:20 PM PDT 24
Peak memory	215688 kb
Host	smart-2d0923a5-a40a-4c22-81ae-819a49ecadaa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529130624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2529130624 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.kmac_intr_test.3792381168
Short name	T1093
Test name
Test status
Simulation time	16504994 ps
CPU time	0.78 seconds
Started	Jun 04 12:46:24 PM PDT 24
Finished	Jun 04 12:46:26 PM PDT 24
Peak memory	215720 kb
Host	smart-88e1732d-0e29-41c9-ac71-2b19e2da8f40
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792381168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3792381168 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1822900747
Short name	T1111
Test name
Test status
Simulation time	73113165 ps
CPU time	2.68 seconds
Started	Jun 04 12:45:58 PM PDT 24
Finished	Jun 04 12:46:02 PM PDT 24
Peak memory	220956 kb
Host	smart-685a57c0-1722-43a1-91b8-ed3cecf5a83f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822900747 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.1822900747 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.159015062
Short name	T1160
Test name
Test status
Simulation time	23414243 ps
CPU time	0.96 seconds
Started	Jun 04 12:45:59 PM PDT 24
Finished	Jun 04 12:46:02 PM PDT 24
Peak memory	215800 kb
Host	smart-f0d4f408-678e-4e30-b26a-9be0fd16d670
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159015062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.159015062 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_intr_test.1252140039
Short name	T1117
Test name
Test status
Simulation time	16253338 ps
CPU time	0.84 seconds
Started	Jun 04 12:45:57 PM PDT 24
Finished	Jun 04 12:45:59 PM PDT 24
Peak memory	215688 kb
Host	smart-0666532d-ef16-45d2-a39a-690377fe6d3c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252140039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1252140039 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2065442692
Short name	T1159
Test name
Test status
Simulation time	281990222 ps
CPU time	1.74 seconds
Started	Jun 04 12:46:07 PM PDT 24
Finished	Jun 04 12:46:09 PM PDT 24
Peak memory	215960 kb
Host	smart-253bf058-b201-46fa-8308-9c3111377e59
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065442692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr _outstanding.2065442692 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2688403330
Short name	T1147
Test name
Test status
Simulation time	41235471 ps
CPU time	1.21 seconds
Started	Jun 04 12:45:59 PM PDT 24
Finished	Jun 04 12:46:02 PM PDT 24
Peak memory	216540 kb
Host	smart-00def11a-8691-4993-9f60-0f739f1027b1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688403330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_ errors.2688403330 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3001580532
Short name	T1106
Test name
Test status
Simulation time	141801176 ps
CPU time	2.47 seconds
Started	Jun 04 12:45:57 PM PDT 24
Finished	Jun 04 12:46:01 PM PDT 24
Peak memory	218840 kb
Host	smart-e5d1ddc8-7468-4abf-8d41-a2dda3fcdb6d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001580532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac _shadow_reg_errors_with_csr_rw.3001580532 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.1313139558
Short name	T1122
Test name
Test status
Simulation time	63763588 ps
CPU time	1.13 seconds
Started	Jun 04 12:45:58 PM PDT 24
Finished	Jun 04 12:46:01 PM PDT 24
Peak memory	216044 kb
Host	smart-8945d661-49ce-4b39-951e-89c00077efc2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313139558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.1313139558 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.3365458058
Short name	T173
Test name
Test status
Simulation time	192175182 ps
CPU time	2.6 seconds
Started	Jun 04 12:45:57 PM PDT 24
Finished	Jun 04 12:46:02 PM PDT 24
Peak memory	215980 kb
Host	smart-a8662c47-c7ce-49a3-a93e-f8118a3bdadb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365458058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.33654 58058 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.983902964
Short name	T1100
Test name
Test status
Simulation time	22415728 ps
CPU time	1.57 seconds
Started	Jun 04 12:45:58 PM PDT 24
Finished	Jun 04 12:46:02 PM PDT 24
Peak memory	219516 kb
Host	smart-d3972f5b-79e5-46cf-aa95-d1d27ba90a73
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983902964 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.983902964 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.547857354
Short name	T1195
Test name
Test status
Simulation time	55121684 ps
CPU time	1.17 seconds
Started	Jun 04 12:45:59 PM PDT 24
Finished	Jun 04 12:46:01 PM PDT 24
Peak memory	215964 kb
Host	smart-fd28a1db-a670-402f-a10d-4fd3b80d74af
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547857354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.547857354 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_intr_test.1180892941
Short name	T1194
Test name
Test status
Simulation time	18179693 ps
CPU time	0.84 seconds
Started	Jun 04 12:46:07 PM PDT 24
Finished	Jun 04 12:46:08 PM PDT 24
Peak memory	215680 kb
Host	smart-96737c9f-2f6e-46c6-b2d8-006368dffe43
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180892941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.1180892941 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.762428299
Short name	T1206
Test name
Test status
Simulation time	76845302 ps
CPU time	1.48 seconds
Started	Jun 04 12:45:59 PM PDT 24
Finished	Jun 04 12:46:03 PM PDT 24
Peak memory	216000 kb
Host	smart-bba638ee-189a-4600-896a-05dcddf3f03b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762428299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_ outstanding.762428299 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.981188750
Short name	T89
Test name
Test status
Simulation time	15871883 ps
CPU time	0.84 seconds
Started	Jun 04 12:45:57 PM PDT 24
Finished	Jun 04 12:45:59 PM PDT 24
Peak memory	215708 kb
Host	smart-2ac2d8ca-f3c2-4b25-b472-fe05c70e88cc
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981188750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_e rrors.981188750 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.553801506
Short name	T1177
Test name
Test status
Simulation time	128398717 ps
CPU time	1.75 seconds
Started	Jun 04 12:45:57 PM PDT 24
Finished	Jun 04 12:46:00 PM PDT 24
Peak memory	215972 kb
Host	smart-6195cee9-78d2-4357-aadf-91ede9eed17f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553801506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_ shadow_reg_errors_with_csr_rw.553801506 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.2600511432
Short name	T1102
Test name
Test status
Simulation time	96007039 ps
CPU time	2.07 seconds
Started	Jun 04 12:45:59 PM PDT 24
Finished	Jun 04 12:46:03 PM PDT 24
Peak memory	215968 kb
Host	smart-a1b481a4-e08c-4e10-8f7c-b83427d31822
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600511432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.2600511432 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.528837490
Short name	T1203
Test name
Test status
Simulation time	35654683 ps
CPU time	1.46 seconds
Started	Jun 04 12:46:07 PM PDT 24
Finished	Jun 04 12:46:10 PM PDT 24
Peak memory	219304 kb
Host	smart-4e9da57f-43c5-4ebc-9356-1e703374164f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528837490 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.528837490 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.367510338
Short name	T1094
Test name
Test status
Simulation time	88649527 ps
CPU time	1.14 seconds
Started	Jun 04 12:46:11 PM PDT 24
Finished	Jun 04 12:46:14 PM PDT 24
Peak memory	215956 kb
Host	smart-682dca3a-aaf8-4fde-b41e-4c7bdfef5893
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367510338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.367510338 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_intr_test.3138596577
Short name	T1179
Test name
Test status
Simulation time	41848699 ps
CPU time	0.79 seconds
Started	Jun 04 12:45:59 PM PDT 24
Finished	Jun 04 12:46:01 PM PDT 24
Peak memory	215660 kb
Host	smart-7760cea4-31c5-4b71-b5c0-d3efa11c37ee
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138596577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3138596577 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3902625647
Short name	T1235
Test name
Test status
Simulation time	523067201 ps
CPU time	2.24 seconds
Started	Jun 04 12:46:06 PM PDT 24
Finished	Jun 04 12:46:09 PM PDT 24
Peak memory	216024 kb
Host	smart-5d0841ef-08ec-4d64-b130-48106d8c93b7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902625647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr _outstanding.3902625647 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1475596854
Short name	T92
Test name
Test status
Simulation time	18643392 ps
CPU time	0.98 seconds
Started	Jun 04 12:45:58 PM PDT 24
Finished	Jun 04 12:46:01 PM PDT 24
Peak memory	215768 kb
Host	smart-3481a3a1-8f7c-4ad2-a7ad-6f4c7305c5a9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475596854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_ errors.1475596854 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.742246468
Short name	T1165
Test name
Test status
Simulation time	509824870 ps
CPU time	1.92 seconds
Started	Jun 04 12:45:58 PM PDT 24
Finished	Jun 04 12:46:02 PM PDT 24
Peak memory	216272 kb
Host	smart-b77e1f86-c198-488c-bc18-119ffe2b8274
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742246468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_ shadow_reg_errors_with_csr_rw.742246468 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.952433910
Short name	T1244
Test name
Test status
Simulation time	315959756 ps
CPU time	2.9 seconds
Started	Jun 04 12:45:57 PM PDT 24
Finished	Jun 04 12:46:02 PM PDT 24
Peak memory	216060 kb
Host	smart-6cbf229b-86e2-4b14-8f8a-7b5d6d80c728
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952433910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.952433910 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1775096233
Short name	T1170
Test name
Test status
Simulation time	875638218 ps
CPU time	5.12 seconds
Started	Jun 04 12:45:59 PM PDT 24
Finished	Jun 04 12:46:06 PM PDT 24
Peak memory	215928 kb
Host	smart-fe46178a-1484-4f10-9254-24d0f44a8621
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775096233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.17750 96233 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.3595894470
Short name	T1198
Test name
Test status
Simulation time	142716535 ps
CPU time	2.43 seconds
Started	Jun 04 12:46:07 PM PDT 24
Finished	Jun 04 12:46:10 PM PDT 24
Peak memory	222096 kb
Host	smart-03e33056-16ad-4ca1-8d71-9459d28e5f21
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595894470 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.3595894470 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.3952523919
Short name	T148
Test name
Test status
Simulation time	30757918 ps
CPU time	1.27 seconds
Started	Jun 04 12:46:07 PM PDT 24
Finished	Jun 04 12:46:10 PM PDT 24
Peak memory	215844 kb
Host	smart-060f3a8a-a2c6-43ab-a0a5-f89a269bdc86
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952523919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3952523919 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_intr_test.3421429942
Short name	T1250
Test name
Test status
Simulation time	11064661 ps
CPU time	0.75 seconds
Started	Jun 04 12:46:07 PM PDT 24
Finished	Jun 04 12:46:08 PM PDT 24
Peak memory	215736 kb
Host	smart-b00a727b-0bd9-4367-b3fc-7bae16c5096f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421429942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3421429942 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.789597713
Short name	T1181
Test name
Test status
Simulation time	51090381 ps
CPU time	1.56 seconds
Started	Jun 04 12:46:05 PM PDT 24
Finished	Jun 04 12:46:08 PM PDT 24
Peak memory	215884 kb
Host	smart-c5524bd3-732a-423f-8baf-c2e09c471cce
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789597713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_ outstanding.789597713 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.289755791
Short name	T88
Test name
Test status
Simulation time	48291541 ps
CPU time	1.31 seconds
Started	Jun 04 12:46:07 PM PDT 24
Finished	Jun 04 12:46:10 PM PDT 24
Peak memory	215916 kb
Host	smart-2ffbf0b4-ca01-42d3-bdda-1d260dd7eedd
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289755791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_e rrors.289755791 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2799667009
Short name	T1214
Test name
Test status
Simulation time	501448309 ps
CPU time	3.19 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:14 PM PDT 24
Peak memory	219836 kb
Host	smart-34fe310e-850c-4f69-819c-3f931619dbce
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799667009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac _shadow_reg_errors_with_csr_rw.2799667009 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.920031036
Short name	T1138
Test name
Test status
Simulation time	42147584 ps
CPU time	1.44 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:12 PM PDT 24
Peak memory	216156 kb
Host	smart-97e0a280-23ad-4da2-abd7-63722f3b0e11
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920031036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.920031036 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.796531380
Short name	T126
Test name
Test status
Simulation time	102280233 ps
CPU time	4.08 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:15 PM PDT 24
Peak memory	215968 kb
Host	smart-ac7ef520-319c-4cbc-a35b-66cad9b54a3b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796531380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.796531 380 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.4023595487
Short name	T1227
Test name
Test status
Simulation time	274847553 ps
CPU time	1.55 seconds
Started	Jun 04 12:46:06 PM PDT 24
Finished	Jun 04 12:46:09 PM PDT 24
Peak memory	219680 kb
Host	smart-129aeedd-8cf2-40f3-83de-d7e3852a62e7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023595487 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.4023595487 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.1668449922
Short name	T1118
Test name
Test status
Simulation time	13284466 ps
CPU time	0.96 seconds
Started	Jun 04 12:46:08 PM PDT 24
Finished	Jun 04 12:46:11 PM PDT 24
Peak memory	215728 kb
Host	smart-d27e3eb5-8cca-4809-981f-6d0192e56295
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668449922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.1668449922 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_intr_test.2355773298
Short name	T1168
Test name
Test status
Simulation time	25176251 ps
CPU time	0.84 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:12 PM PDT 24
Peak memory	215668 kb
Host	smart-ac948f5b-0b6a-4e72-8619-3003b4fea71a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355773298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.2355773298 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2474131446
Short name	T1152
Test name
Test status
Simulation time	86973321 ps
CPU time	2.5 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:14 PM PDT 24
Peak memory	215992 kb
Host	smart-d44246a9-f104-439d-83fe-fec8111dd1e1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474131446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr _outstanding.2474131446 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3644117596
Short name	T101
Test name
Test status
Simulation time	117522757 ps
CPU time	1.74 seconds
Started	Jun 04 12:46:06 PM PDT 24
Finished	Jun 04 12:46:09 PM PDT 24
Peak memory	216304 kb
Host	smart-a40c2f6d-c2a1-4a27-9464-71a362906ed0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644117596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_ errors.3644117596 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1770625786
Short name	T98
Test name
Test status
Simulation time	238028063 ps
CPU time	3.14 seconds
Started	Jun 04 12:46:09 PM PDT 24
Finished	Jun 04 12:46:14 PM PDT 24
Peak memory	218280 kb
Host	smart-af0cbd2a-e8ab-45aa-8846-cd9c46ef9b43
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770625786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac _shadow_reg_errors_with_csr_rw.1770625786 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.508636008
Short name	T1212
Test name
Test status
Simulation time	112432567 ps
CPU time	1.84 seconds
Started	Jun 04 12:46:11 PM PDT 24
Finished	Jun 04 12:46:15 PM PDT 24
Peak memory	216068 kb
Host	smart-626e7b68-d625-482d-99ca-7c082be4b28e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508636008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.508636008 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.4166403277
Short name	T128
Test name
Test status
Simulation time	432870601 ps
CPU time	2.8 seconds
Started	Jun 04 12:46:07 PM PDT 24
Finished	Jun 04 12:46:11 PM PDT 24
Peak memory	216072 kb
Host	smart-d854a232-d8ec-464c-82c9-888bf03769aa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166403277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.41664 03277 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/0.kmac_alert_test.2589202070
Short name	T716
Test name
Test status
Simulation time	61587059 ps
CPU time	0.87 seconds
Started	Jun 04 02:23:27 PM PDT 24
Finished	Jun 04 02:23:29 PM PDT 24
Peak memory	218936 kb
Host	smart-47408ab1-c144-4b33-91b2-55030bfb7cce
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589202070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.2589202070 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_alert_test/latest

Test location	/workspace/coverage/default/0.kmac_app.614022661
Short name	T708
Test name
Test status
Simulation time	95384266658 ps
CPU time	404.03 seconds
Started	Jun 04 02:23:15 PM PDT 24
Finished	Jun 04 02:30:00 PM PDT 24
Peak memory	250448 kb
Host	smart-a253efec-88e1-4a9b-9a29-ea680ad2b6d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=614022661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.614022661 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_app/latest

Test location	/workspace/coverage/default/0.kmac_app_with_partial_data.1125978540
Short name	T719
Test name
Test status
Simulation time	476025947 ps
CPU time	9.11 seconds
Started	Jun 04 02:23:21 PM PDT 24
Finished	Jun 04 02:23:31 PM PDT 24
Peak memory	227368 kb
Host	smart-cf31bac9-f749-422b-9433-0c27e74e0e88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1125978540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.1125978540 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/0.kmac_burst_write.1099135218
Short name	T145
Test name
Test status
Simulation time	42688626545 ps
CPU time	1088.86 seconds
Started	Jun 04 02:23:23 PM PDT 24
Finished	Jun 04 02:41:32 PM PDT 24
Peak memory	238208 kb
Host	smart-826efd13-9154-4988-970d-3fd5f67b44fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1099135218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.1099135218 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_burst_write/latest

Test location	/workspace/coverage/default/0.kmac_entropy_mode_error.1196849290
Short name	T602
Test name
Test status
Simulation time	82647909 ps
CPU time	1.12 seconds
Started	Jun 04 02:23:19 PM PDT 24
Finished	Jun 04 02:23:21 PM PDT 24
Peak memory	222784 kb
Host	smart-33c124a5-64a6-492f-99ef-6a3931d3e41d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1196849290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.1196849290 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/0.kmac_entropy_ready_error.332244578
Short name	T1074
Test name
Test status
Simulation time	6838345139 ps
CPU time	71.32 seconds
Started	Jun 04 02:23:23 PM PDT 24
Finished	Jun 04 02:24:35 PM PDT 24
Peak memory	227468 kb
Host	smart-60d94765-411c-4cc7-b424-471d37548117
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=332244578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.332244578 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspace/0.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/0.kmac_entropy_refresh.809076050
Short name	T666
Test name
Test status
Simulation time	47649595339 ps
CPU time	210.6 seconds
Started	Jun 04 02:23:20 PM PDT 24
Finished	Jun 04 02:26:51 PM PDT 24
Peak memory	240868 kb
Host	smart-688d1e50-5c02-42c3-b0de-a07e5f72bc97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=809076050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.809076050 +enable_masking=1 +sw_ key_masked=0
Directory	/workspace/0.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/0.kmac_error.1786077436
Short name	T20
Test name
Test status
Simulation time	7010098190 ps
CPU time	251.57 seconds
Started	Jun 04 02:23:21 PM PDT 24
Finished	Jun 04 02:27:33 PM PDT 24
Peak memory	260244 kb
Host	smart-348e5e3f-9dce-49bf-b2ce-41937233a0f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1786077436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.1786077436 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_error/latest

Test location	/workspace/coverage/default/0.kmac_key_error.2790628652
Short name	T813
Test name
Test status
Simulation time	3452160376 ps
CPU time	7.93 seconds
Started	Jun 04 02:23:20 PM PDT 24
Finished	Jun 04 02:23:29 PM PDT 24
Peak memory	225768 kb
Host	smart-f19519ff-2b75-4a64-8c0f-23e25ffbbfae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2790628652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.2790628652 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_key_error/latest

Test location	/workspace/coverage/default/0.kmac_lc_escalation.2439607961
Short name	T1049
Test name
Test status
Simulation time	53708449 ps
CPU time	1.25 seconds
Started	Jun 04 02:23:22 PM PDT 24
Finished	Jun 04 02:23:24 PM PDT 24
Peak memory	227320 kb
Host	smart-ebe6c617-f0ec-4e66-86fd-048ac5cecef1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2439607961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2439607961 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/0.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/0.kmac_long_msg_and_output.4262404415
Short name	T250
Test name
Test status
Simulation time	38884005918 ps
CPU time	977.12 seconds
Started	Jun 04 02:23:19 PM PDT 24
Finished	Jun 04 02:39:37 PM PDT 24
Peak memory	296756 kb
Host	smart-a2c522ee-28f4-4e80-83a2-7dada1d10498
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262404415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an d_output.4262404415 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/0.kmac_mubi.1845827395
Short name	T939
Test name
Test status
Simulation time	71115200252 ps
CPU time	209.52 seconds
Started	Jun 04 02:23:20 PM PDT 24
Finished	Jun 04 02:26:50 PM PDT 24
Peak memory	243468 kb
Host	smart-69d546a8-5503-4f13-9080-7c9422ade9fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1845827395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.1845827395 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_mubi/latest

Test location	/workspace/coverage/default/0.kmac_sec_cm.1002715752
Short name	T83
Test name
Test status
Simulation time	9894669993 ps
CPU time	37.13 seconds
Started	Jun 04 02:23:28 PM PDT 24
Finished	Jun 04 02:24:05 PM PDT 24
Peak memory	257344 kb
Host	smart-ce571e2b-7747-460c-9e0b-a9addec823dd
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002715752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1002715752 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/0.kmac_sec_cm/latest

Test location	/workspace/coverage/default/0.kmac_sideload.1091256558
Short name	T857
Test name
Test status
Simulation time	15893612037 ps
CPU time	376.06 seconds
Started	Jun 04 02:23:22 PM PDT 24
Finished	Jun 04 02:29:39 PM PDT 24
Peak memory	249108 kb
Host	smart-4b908ab0-da34-4a11-bce9-232ec009bc74
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091256558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1091256558 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_sideload/latest

Test location	/workspace/coverage/default/0.kmac_smoke.2425627492
Short name	T650
Test name
Test status
Simulation time	523139203 ps
CPU time	5.84 seconds
Started	Jun 04 02:23:19 PM PDT 24
Finished	Jun 04 02:23:26 PM PDT 24
Peak memory	219636 kb
Host	smart-54f6c63d-1212-4962-8417-c0d63e47568e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2425627492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2425627492 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_smoke/latest

Test location	/workspace/coverage/default/0.kmac_stress_all.2001166710
Short name	T642
Test name
Test status
Simulation time	122965302267 ps
CPU time	1007.72 seconds
Started	Jun 04 02:23:22 PM PDT 24
Finished	Jun 04 02:40:10 PM PDT 24
Peak memory	338900 kb
Host	smart-d2010314-52f7-4668-9d3f-864d3d08012d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2001166710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.2001166710 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_stress_all/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_kmac.976328586
Short name	T272
Test name
Test status
Simulation time	434299754 ps
CPU time	5.63 seconds
Started	Jun 04 02:23:19 PM PDT 24
Finished	Jun 04 02:23:25 PM PDT 24
Peak memory	219332 kb
Host	smart-03f38fb3-861a-4ebf-83df-529601b1c706
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976328586 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.kmac_test_vectors_kmac.976328586 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_kmac_xof.3463567746
Short name	T256
Test name
Test status
Simulation time	220599468 ps
CPU time	6.53 seconds
Started	Jun 04 02:23:14 PM PDT 24
Finished	Jun 04 02:23:21 PM PDT 24
Peak memory	219292 kb
Host	smart-54f6420f-5341-4433-8f78-b51ed2c200a0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463567746 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.3463567746 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_224.97115050
Short name	T264
Test name
Test status
Simulation time	20937422048 ps
CPU time	2201.12 seconds
Started	Jun 04 02:23:20 PM PDT 24
Finished	Jun 04 03:00:02 PM PDT 24
Peak memory	408700 kb
Host	smart-7a6d6439-02f5-4b12-a6f8-102c43f12e89
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=97115050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.97115050 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_256.3405097585
Short name	T469
Test name
Test status
Simulation time	208615034337 ps
CPU time	1982.46 seconds
Started	Jun 04 02:23:19 PM PDT 24
Finished	Jun 04 02:56:23 PM PDT 24
Peak memory	380444 kb
Host	smart-065de970-8b4c-4779-a908-266bcdbeefd4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3405097585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.3405097585 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_384.1084940922
Short name	T159
Test name
Test status
Simulation time	162363163151 ps
CPU time	1438.76 seconds
Started	Jun 04 02:23:16 PM PDT 24
Finished	Jun 04 02:47:15 PM PDT 24
Peak memory	334408 kb
Host	smart-3f49d238-b37a-4a47-889d-280f111c776d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1084940922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.1084940922 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_512.8102170
Short name	T884
Test name
Test status
Simulation time	200552945164 ps
CPU time	1289.62 seconds
Started	Jun 04 02:23:16 PM PDT 24
Finished	Jun 04 02:44:47 PM PDT 24
Peak memory	304624 kb
Host	smart-644dd2e0-b7c0-4cd0-93b9-489abbfd91e2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=8102170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.8102170 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_shake_128.3602524466
Short name	T932
Test name
Test status
Simulation time	1025864206168 ps
CPU time	6297.92 seconds
Started	Jun 04 02:23:24 PM PDT 24
Finished	Jun 04 04:08:23 PM PDT 24
Peak memory	649976 kb
Host	smart-59fadec8-b1c4-4fd3-ad92-cbc25f67acd8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3602524466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.3602524466 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_shake_256.4102083114
Short name	T228
Test name
Test status
Simulation time	205608915523 ps
CPU time	4518.6 seconds
Started	Jun 04 02:23:19 PM PDT 24
Finished	Jun 04 03:38:39 PM PDT 24
Peak memory	580980 kb
Host	smart-56759873-0040-4919-9e17-7584cfa24110
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4102083114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.4102083114 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/1.kmac_app.3228747823
Short name	T956
Test name
Test status
Simulation time	8431105153 ps
CPU time	225.79 seconds
Started	Jun 04 02:23:24 PM PDT 24
Finished	Jun 04 02:27:11 PM PDT 24
Peak memory	245708 kb
Host	smart-9ed20fd8-830a-4812-95e4-f27c4abfbc9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3228747823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.3228747823 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_app/latest

Test location	/workspace/coverage/default/1.kmac_app_with_partial_data.3218211622
Short name	T1071
Test name
Test status
Simulation time	11105065343 ps
CPU time	283.77 seconds
Started	Jun 04 02:23:29 PM PDT 24
Finished	Jun 04 02:28:14 PM PDT 24
Peak memory	247688 kb
Host	smart-11fcd635-6fae-4f62-8ed4-930eb3966793
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3218211622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.3218211622 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/1.kmac_burst_write.1225610927
Short name	T302
Test name
Test status
Simulation time	12650809938 ps
CPU time	436.26 seconds
Started	Jun 04 02:23:22 PM PDT 24
Finished	Jun 04 02:30:40 PM PDT 24
Peak memory	232984 kb
Host	smart-691fd6ad-c491-49b7-b786-39933877cba4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1225610927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.1225610927 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_burst_write/latest

Test location	/workspace/coverage/default/1.kmac_edn_timeout_error.2015103773
Short name	T985
Test name
Test status
Simulation time	26989446 ps
CPU time	0.93 seconds
Started	Jun 04 02:23:34 PM PDT 24
Finished	Jun 04 02:23:36 PM PDT 24
Peak memory	222096 kb
Host	smart-4eaa0646-dc10-46de-aca8-fae2e4a72716
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2015103773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.2015103773 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_mode_error.125778709
Short name	T626
Test name
Test status
Simulation time	33182085 ps
CPU time	1.15 seconds
Started	Jun 04 02:23:35 PM PDT 24
Finished	Jun 04 02:23:37 PM PDT 24
Peak memory	222712 kb
Host	smart-38e39083-4cb5-448d-a92c-9080bcd9cd6b
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=125778709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.125778709 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_ready_error.2156577505
Short name	T665
Test name
Test status
Simulation time	22768143914 ps
CPU time	78.94 seconds
Started	Jun 04 02:23:31 PM PDT 24
Finished	Jun 04 02:24:51 PM PDT 24
Peak memory	227496 kb
Host	smart-dbdb6059-e308-4837-96c8-ef18466fed3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156577505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.2156577505 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/1.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_refresh.4102895826
Short name	T1008
Test name
Test status
Simulation time	15689709596 ps
CPU time	145.04 seconds
Started	Jun 04 02:23:27 PM PDT 24
Finished	Jun 04 02:25:52 PM PDT 24
Peak memory	238208 kb
Host	smart-fdd23cb5-e3ff-4710-85d9-3da61d9399d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4102895826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.4102895826 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/1.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/1.kmac_error.317276070
Short name	T465
Test name
Test status
Simulation time	11043588134 ps
CPU time	243.18 seconds
Started	Jun 04 02:23:30 PM PDT 24
Finished	Jun 04 02:27:34 PM PDT 24
Peak memory	260224 kb
Host	smart-71a57c10-9d76-49d8-be56-ea849a66ecf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=317276070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.317276070 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_error/latest

Test location	/workspace/coverage/default/1.kmac_key_error.3058831337
Short name	T4
Test name
Test status
Simulation time	1427998704 ps
CPU time	10.87 seconds
Started	Jun 04 02:23:34 PM PDT 24
Finished	Jun 04 02:23:46 PM PDT 24
Peak memory	224684 kb
Host	smart-45bb83b3-86aa-44c0-a3c8-ea474b26a1c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3058831337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.3058831337 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_key_error/latest

Test location	/workspace/coverage/default/1.kmac_long_msg_and_output.3492921924
Short name	T235
Test name
Test status
Simulation time	25403839214 ps
CPU time	2682.02 seconds
Started	Jun 04 02:23:25 PM PDT 24
Finished	Jun 04 03:08:08 PM PDT 24
Peak memory	450384 kb
Host	smart-9f24261f-3584-4e86-be83-199dfb495f5f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492921924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an d_output.3492921924 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/1.kmac_mubi.2272580838
Short name	T794
Test name
Test status
Simulation time	2550967892 ps
CPU time	84.62 seconds
Started	Jun 04 02:23:29 PM PDT 24
Finished	Jun 04 02:24:55 PM PDT 24
Peak memory	231816 kb
Host	smart-ee056cff-1933-4ec6-be5e-39345e438bfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2272580838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.2272580838 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_mubi/latest

Test location	/workspace/coverage/default/1.kmac_sec_cm.1703160710
Short name	T12
Test name
Test status
Simulation time	8154663995 ps
CPU time	60.8 seconds
Started	Jun 04 02:23:34 PM PDT 24
Finished	Jun 04 02:24:36 PM PDT 24
Peak memory	266000 kb
Host	smart-855620af-9a3e-4abf-bdae-abf1b6205e8e
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703160710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1703160710 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/1.kmac_sec_cm/latest

Test location	/workspace/coverage/default/1.kmac_sideload.2339280711
Short name	T386
Test name
Test status
Simulation time	7024212813 ps
CPU time	140.05 seconds
Started	Jun 04 02:23:23 PM PDT 24
Finished	Jun 04 02:25:44 PM PDT 24
Peak memory	236376 kb
Host	smart-61641614-ef3d-44aa-ab6d-b5a5e30c1b57
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339280711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.2339280711 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_sideload/latest

Test location	/workspace/coverage/default/1.kmac_smoke.2918747561
Short name	T483
Test name
Test status
Simulation time	511352109 ps
CPU time	15.99 seconds
Started	Jun 04 02:23:24 PM PDT 24
Finished	Jun 04 02:23:41 PM PDT 24
Peak memory	225480 kb
Host	smart-78cefa91-a8ed-478c-a8f2-f052f26a2ccb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2918747561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.2918747561 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_smoke/latest

Test location	/workspace/coverage/default/1.kmac_stress_all.4094294159
Short name	T369
Test name
Test status
Simulation time	89749814213 ps
CPU time	1528.02 seconds
Started	Jun 04 02:23:34 PM PDT 24
Finished	Jun 04 02:49:03 PM PDT 24
Peak memory	382524 kb
Host	smart-e6755cd5-b5cc-444d-8ceb-2a57de1202f0
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4094294159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.4094294159 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_stress_all/latest

Test location	/workspace/coverage/default/1.kmac_stress_all_with_rand_reset.3738869184
Short name	T775
Test name
Test status
Simulation time	410519055116 ps
CPU time	2283.02 seconds
Started	Jun 04 02:23:30 PM PDT 24
Finished	Jun 04 03:01:33 PM PDT 24
Peak memory	391652 kb
Host	smart-42bc406e-6c72-405a-aadf-d14438d7e0d4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3738869184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_with_rand_reset.3738869184 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_kmac.1539410295
Short name	T730
Test name
Test status
Simulation time	2538834088 ps
CPU time	6 seconds
Started	Jun 04 02:23:23 PM PDT 24
Finished	Jun 04 02:23:30 PM PDT 24
Peak memory	219388 kb
Host	smart-8b7cb2aa-fc17-49d3-bc03-858a65e744ee
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539410295 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.kmac_test_vectors_kmac.1539410295 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_kmac_xof.2256814955
Short name	T252
Test name
Test status
Simulation time	89322663 ps
CPU time	6.04 seconds
Started	Jun 04 02:23:26 PM PDT 24
Finished	Jun 04 02:23:32 PM PDT 24
Peak memory	220216 kb
Host	smart-886660a3-4a21-4aaa-8590-27ac3bf49a43
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256814955 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.2256814955 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_224.1528246232
Short name	T820
Test name
Test status
Simulation time	31066763201 ps
CPU time	2018.7 seconds
Started	Jun 04 02:23:25 PM PDT 24
Finished	Jun 04 02:57:05 PM PDT 24
Peak memory	403988 kb
Host	smart-964937d9-584b-4704-ae2a-2a1a6eb8d823
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1528246232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.1528246232 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_256.2748605617
Short name	T940
Test name
Test status
Simulation time	350586573951 ps
CPU time	2128.32 seconds
Started	Jun 04 02:23:25 PM PDT 24
Finished	Jun 04 02:58:54 PM PDT 24
Peak memory	364904 kb
Host	smart-50f89286-03bb-4f1a-ac98-60def013dd31
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2748605617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.2748605617 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_384.4218065727
Short name	T328
Test name
Test status
Simulation time	702625998041 ps
CPU time	1807.81 seconds
Started	Jun 04 02:23:27 PM PDT 24
Finished	Jun 04 02:53:36 PM PDT 24
Peak memory	339528 kb
Host	smart-8997ff22-d735-4852-a4c7-8560ef9278fd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4218065727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.4218065727 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_512.3811785173
Short name	T963
Test name
Test status
Simulation time	118319913844 ps
CPU time	1258.62 seconds
Started	Jun 04 02:23:22 PM PDT 24
Finished	Jun 04 02:44:21 PM PDT 24
Peak memory	300944 kb
Host	smart-a391facd-10c9-43ff-b71e-7b46d0a8aabe
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3811785173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.3811785173 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_shake_128.1234539101
Short name	T1061
Test name
Test status
Simulation time	1180104369872 ps
CPU time	6597.11 seconds
Started	Jun 04 02:23:24 PM PDT 24
Finished	Jun 04 04:13:23 PM PDT 24
Peak memory	657384 kb
Host	smart-3586ebd8-d7a3-41dc-ac4f-f2440603de11
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1234539101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1234539101 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_shake_256.1049072371
Short name	T926
Test name
Test status
Simulation time	202828118009 ps
CPU time	5118.05 seconds
Started	Jun 04 02:23:23 PM PDT 24
Finished	Jun 04 03:48:42 PM PDT 24
Peak memory	580908 kb
Host	smart-56785f97-246b-4f75-a135-9e4b6df86022
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1049072371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1049072371 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/10.kmac_alert_test.411032607
Short name	T222
Test name
Test status
Simulation time	56300404 ps
CPU time	0.82 seconds
Started	Jun 04 02:24:49 PM PDT 24
Finished	Jun 04 02:24:51 PM PDT 24
Peak memory	218952 kb
Host	smart-952f7f7b-947b-4e2e-8ab1-c96b25e047ba
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411032607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.411032607 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_alert_test/latest

Test location	/workspace/coverage/default/10.kmac_app.1280453380
Short name	T529
Test name
Test status
Simulation time	4644862422 ps
CPU time	63.94 seconds
Started	Jun 04 02:24:43 PM PDT 24
Finished	Jun 04 02:25:47 PM PDT 24
Peak memory	239416 kb
Host	smart-2420be79-ae1e-49e3-a9d3-a933117ece93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1280453380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1280453380 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_app/latest

Test location	/workspace/coverage/default/10.kmac_burst_write.617393688
Short name	T747
Test name
Test status
Simulation time	62046616108 ps
CPU time	1024.76 seconds
Started	Jun 04 02:24:43 PM PDT 24
Finished	Jun 04 02:41:49 PM PDT 24
Peak memory	243852 kb
Host	smart-40c84b3f-ba58-4040-b22c-e9d8f36a5b19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=617393688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.617393688 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_burst_write/latest

Test location	/workspace/coverage/default/10.kmac_edn_timeout_error.2088819969
Short name	T928
Test name
Test status
Simulation time	67377626 ps
CPU time	0.86 seconds
Started	Jun 04 02:24:48 PM PDT 24
Finished	Jun 04 02:24:49 PM PDT 24
Peak memory	222024 kb
Host	smart-969df8c3-41e6-4a90-9aea-6838b05cdedb
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2088819969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2088819969 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/10.kmac_entropy_mode_error.280096763
Short name	T707
Test name
Test status
Simulation time	22219491 ps
CPU time	0.91 seconds
Started	Jun 04 02:24:50 PM PDT 24
Finished	Jun 04 02:24:51 PM PDT 24
Peak memory	221032 kb
Host	smart-7247fe34-6c38-4f16-b6b5-0a6200bb89ed
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=280096763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.280096763 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/10.kmac_entropy_refresh.1376156479
Short name	T490
Test name
Test status
Simulation time	41042788308 ps
CPU time	229.38 seconds
Started	Jun 04 02:24:49 PM PDT 24
Finished	Jun 04 02:28:39 PM PDT 24
Peak memory	246068 kb
Host	smart-b53f489d-bd18-4dc5-ac3b-ec88d101f86f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1376156479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.1376156479 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/10.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/10.kmac_error.3737716235
Short name	T759
Test name
Test status
Simulation time	19153061807 ps
CPU time	453.7 seconds
Started	Jun 04 02:24:47 PM PDT 24
Finished	Jun 04 02:32:22 PM PDT 24
Peak memory	259792 kb
Host	smart-5269a7d8-126e-4444-87a7-1658b4ea1244
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3737716235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.3737716235 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_error/latest

Test location	/workspace/coverage/default/10.kmac_key_error.1679963247
Short name	T953
Test name
Test status
Simulation time	3365102734 ps
CPU time	6.14 seconds
Started	Jun 04 02:24:50 PM PDT 24
Finished	Jun 04 02:24:57 PM PDT 24
Peak memory	224520 kb
Host	smart-cdc242db-1148-4d2f-8e8a-6fbdf3427716
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1679963247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.1679963247 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_key_error/latest

Test location	/workspace/coverage/default/10.kmac_lc_escalation.3779044128
Short name	T763
Test name
Test status
Simulation time	1574999113 ps
CPU time	21.09 seconds
Started	Jun 04 02:24:51 PM PDT 24
Finished	Jun 04 02:25:13 PM PDT 24
Peak memory	235552 kb
Host	smart-608036d1-d048-43b6-8bbc-90f518682205
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3779044128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.3779044128 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/10.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/10.kmac_long_msg_and_output.1644468458
Short name	T551
Test name
Test status
Simulation time	12578343286 ps
CPU time	1115.13 seconds
Started	Jun 04 02:24:43 PM PDT 24
Finished	Jun 04 02:43:19 PM PDT 24
Peak memory	323400 kb
Host	smart-d10b23ad-216a-4add-9ce3-59fcb5d71ff8
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644468458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a nd_output.1644468458 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/10.kmac_sideload.960030072
Short name	T489
Test name
Test status
Simulation time	7456842700 ps
CPU time	422.69 seconds
Started	Jun 04 02:24:43 PM PDT 24
Finished	Jun 04 02:31:46 PM PDT 24
Peak memory	258624 kb
Host	smart-eba321d8-93ec-44c1-8d22-2685f8ee930c
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960030072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.960030072 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_sideload/latest

Test location	/workspace/coverage/default/10.kmac_smoke.1411744455
Short name	T668
Test name
Test status
Simulation time	29024588146 ps
CPU time	66.22 seconds
Started	Jun 04 02:24:42 PM PDT 24
Finished	Jun 04 02:25:49 PM PDT 24
Peak memory	227508 kb
Host	smart-21a2ac6d-d2e4-4225-8f92-3700b978fb19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1411744455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.1411744455 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_smoke/latest

Test location	/workspace/coverage/default/10.kmac_stress_all.3761715805
Short name	T907
Test name
Test status
Simulation time	9893548589 ps
CPU time	229.76 seconds
Started	Jun 04 02:24:49 PM PDT 24
Finished	Jun 04 02:28:40 PM PDT 24
Peak memory	264816 kb
Host	smart-863521e7-310e-467b-8ed2-f68fa9f7f1a6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3761715805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.3761715805 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_stress_all/latest

Test location	/workspace/coverage/default/10.kmac_stress_all_with_rand_reset.2404086322
Short name	T22
Test name
Test status
Simulation time	34267743035 ps
CPU time	524.63 seconds
Started	Jun 04 02:24:47 PM PDT 24
Finished	Jun 04 02:33:33 PM PDT 24
Peak memory	252092 kb
Host	smart-512cc88f-efd8-49e1-a248-a892b2124f74
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2404086322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all_with_rand_reset.2404086322 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_kmac.44598254
Short name	T210
Test name
Test status
Simulation time	295424232 ps
CPU time	6.13 seconds
Started	Jun 04 02:24:44 PM PDT 24
Finished	Jun 04 02:24:51 PM PDT 24
Peak memory	219244 kb
Host	smart-04b25438-c50e-48aa-825d-da4f146b9938
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44598254 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 10.kmac_test_vectors_kmac.44598254 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_kmac_xof.2240065146
Short name	T32
Test name
Test status
Simulation time	1432117948 ps
CPU time	6.7 seconds
Started	Jun 04 02:24:44 PM PDT 24
Finished	Jun 04 02:24:51 PM PDT 24
Peak memory	219340 kb
Host	smart-7dc006d0-b6f9-42a8-a478-1e4fc7b76876
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240065146 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_kmac_xof.2240065146 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_224.3451861257
Short name	T437
Test name
Test status
Simulation time	66595547852 ps
CPU time	2086.5 seconds
Started	Jun 04 02:24:48 PM PDT 24
Finished	Jun 04 02:59:35 PM PDT 24
Peak memory	402584 kb
Host	smart-48a06959-ae07-44bd-8aa7-f86a8d7d33b4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3451861257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.3451861257 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_256.1179948749
Short name	T706
Test name
Test status
Simulation time	21378733180 ps
CPU time	1883.54 seconds
Started	Jun 04 02:24:42 PM PDT 24
Finished	Jun 04 02:56:07 PM PDT 24
Peak memory	390792 kb
Host	smart-3ecb611d-3dcd-4b7f-962d-291a07289eed
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1179948749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.1179948749 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_384.3434438987
Short name	T190
Test name
Test status
Simulation time	15658913425 ps
CPU time	1476.47 seconds
Started	Jun 04 02:24:47 PM PDT 24
Finished	Jun 04 02:49:24 PM PDT 24
Peak memory	343696 kb
Host	smart-b7019a81-d32f-4c1f-bf42-90b4be20f098
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3434438987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.3434438987 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_512.1652349589
Short name	T1085
Test name
Test status
Simulation time	133203735432 ps
CPU time	1251.34 seconds
Started	Jun 04 02:24:48 PM PDT 24
Finished	Jun 04 02:45:40 PM PDT 24
Peak memory	302652 kb
Host	smart-15a9809b-f084-4a56-a3aa-ac0808876129
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1652349589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.1652349589 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_shake_128.1757764932
Short name	T887
Test name
Test status
Simulation time	193671289182 ps
CPU time	5258.41 seconds
Started	Jun 04 02:24:43 PM PDT 24
Finished	Jun 04 03:52:23 PM PDT 24
Peak memory	655992 kb
Host	smart-c026368c-cac6-4d9c-91a7-defdcb69e152
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1757764932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.1757764932 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_shake_256.887061892
Short name	T888
Test name
Test status
Simulation time	53425075229 ps
CPU time	4298.11 seconds
Started	Jun 04 02:24:44 PM PDT 24
Finished	Jun 04 03:36:23 PM PDT 24
Peak memory	559996 kb
Host	smart-9d7cf17f-fea2-4aa1-936a-ce6144f4733e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=887061892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.887061892 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/11.kmac_alert_test.1872974202
Short name	T968
Test name
Test status
Simulation time	61172519 ps
CPU time	0.87 seconds
Started	Jun 04 02:25:09 PM PDT 24
Finished	Jun 04 02:25:10 PM PDT 24
Peak memory	218924 kb
Host	smart-be852db6-84d7-412d-b655-48661cc9c6db
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872974202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.1872974202 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_alert_test/latest

Test location	/workspace/coverage/default/11.kmac_app.4094215395
Short name	T279
Test name
Test status
Simulation time	5459598629 ps
CPU time	426.11 seconds
Started	Jun 04 02:24:56 PM PDT 24
Finished	Jun 04 02:32:03 PM PDT 24
Peak memory	254384 kb
Host	smart-6c01a74d-4442-455d-b3c0-4645e355df95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4094215395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.4094215395 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_app/latest

Test location	/workspace/coverage/default/11.kmac_burst_write.3445485341
Short name	T752
Test name
Test status
Simulation time	7871040645 ps
CPU time	53.44 seconds
Started	Jun 04 02:24:57 PM PDT 24
Finished	Jun 04 02:25:51 PM PDT 24
Peak memory	221764 kb
Host	smart-ea28b5b0-5305-4e26-b2b1-07c85b512d4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3445485341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.3445485341 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_burst_write/latest

Test location	/workspace/coverage/default/11.kmac_edn_timeout_error.210238117
Short name	T64
Test name
Test status
Simulation time	74087242 ps
CPU time	1.11 seconds
Started	Jun 04 02:25:02 PM PDT 24
Finished	Jun 04 02:25:04 PM PDT 24
Peak memory	223548 kb
Host	smart-9e580f19-7df3-4414-8fdf-bdea9894759e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=210238117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.210238117 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/11.kmac_error.4269213165
Short name	T523
Test name
Test status
Simulation time	29137202898 ps
CPU time	406.72 seconds
Started	Jun 04 02:25:03 PM PDT 24
Finished	Jun 04 02:31:51 PM PDT 24
Peak memory	260256 kb
Host	smart-500dac73-2efc-4930-a8e2-d0bed7425f89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4269213165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.4269213165 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_error/latest

Test location	/workspace/coverage/default/11.kmac_key_error.1915224686
Short name	T557
Test name
Test status
Simulation time	2033802784 ps
CPU time	2.92 seconds
Started	Jun 04 02:25:02 PM PDT 24
Finished	Jun 04 02:25:06 PM PDT 24
Peak memory	223280 kb
Host	smart-4aca89af-2d3e-4c3b-a035-9654bf8b730b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1915224686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.1915224686 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_key_error/latest

Test location	/workspace/coverage/default/11.kmac_long_msg_and_output.318462383
Short name	T773
Test name
Test status
Simulation time	20781745819 ps
CPU time	520.31 seconds
Started	Jun 04 02:24:58 PM PDT 24
Finished	Jun 04 02:33:39 PM PDT 24
Peak memory	271484 kb
Host	smart-d9451d11-e3b0-4c6b-95eb-46d5e8ff5a2e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318462383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_an d_output.318462383 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/11.kmac_sideload.3645992397
Short name	T357
Test name
Test status
Simulation time	42496100881 ps
CPU time	142.42 seconds
Started	Jun 04 02:24:56 PM PDT 24
Finished	Jun 04 02:27:19 PM PDT 24
Peak memory	236164 kb
Host	smart-5b27f3b8-3992-4155-8f00-c1db4655ae43
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645992397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.3645992397 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_sideload/latest

Test location	/workspace/coverage/default/11.kmac_smoke.431453327
Short name	T197
Test name
Test status
Simulation time	310159178 ps
CPU time	7 seconds
Started	Jun 04 02:24:49 PM PDT 24
Finished	Jun 04 02:24:57 PM PDT 24
Peak memory	219288 kb
Host	smart-47d7d2df-eaf9-4de5-bb7d-dd8101c8ad9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=431453327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.431453327 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_smoke/latest

Test location	/workspace/coverage/default/11.kmac_stress_all.1973267405
Short name	T316
Test name
Test status
Simulation time	43911647391 ps
CPU time	821.94 seconds
Started	Jun 04 02:25:10 PM PDT 24
Finished	Jun 04 02:38:52 PM PDT 24
Peak memory	310216 kb
Host	smart-cfbbd6fa-03f7-4332-a793-c02eaa748334
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1973267405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.1973267405 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_stress_all/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_kmac.360725498
Short name	T731
Test name
Test status
Simulation time	224619277 ps
CPU time	5.91 seconds
Started	Jun 04 02:24:56 PM PDT 24
Finished	Jun 04 02:25:02 PM PDT 24
Peak memory	219220 kb
Host	smart-0767a07b-1131-4d31-b6bb-a6e31d3c9aff
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360725498 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 11.kmac_test_vectors_kmac.360725498 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_kmac_xof.904051623
Short name	T1079
Test name
Test status
Simulation time	290358765 ps
CPU time	6.63 seconds
Started	Jun 04 02:24:56 PM PDT 24
Finished	Jun 04 02:25:03 PM PDT 24
Peak memory	219264 kb
Host	smart-5583ff03-f20b-4b6c-ae41-11d4c5d46e97
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904051623 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 11.kmac_test_vectors_kmac_xof.904051623 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_224.1766406912
Short name	T715
Test name
Test status
Simulation time	65604621322 ps
CPU time	2172.23 seconds
Started	Jun 04 02:24:56 PM PDT 24
Finished	Jun 04 03:01:09 PM PDT 24
Peak memory	393964 kb
Host	smart-e74973c2-299f-4502-91b8-da664bccc246
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1766406912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.1766406912 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_256.2290096970
Short name	T770
Test name
Test status
Simulation time	73129438921 ps
CPU time	2021.46 seconds
Started	Jun 04 02:24:55 PM PDT 24
Finished	Jun 04 02:58:38 PM PDT 24
Peak memory	382596 kb
Host	smart-729122c8-ed06-457d-8a14-821e8ecf7aac
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2290096970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.2290096970 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_384.1631980999
Short name	T221
Test name
Test status
Simulation time	18243175930 ps
CPU time	1508.63 seconds
Started	Jun 04 02:24:57 PM PDT 24
Finished	Jun 04 02:50:06 PM PDT 24
Peak memory	338188 kb
Host	smart-b477e801-3c57-4abc-b9ea-df29fe915533
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1631980999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.1631980999 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_512.3339457158
Short name	T248
Test name
Test status
Simulation time	34416785349 ps
CPU time	1200.62 seconds
Started	Jun 04 02:24:57 PM PDT 24
Finished	Jun 04 02:44:59 PM PDT 24
Peak memory	302872 kb
Host	smart-b2111e16-96bc-48b0-8bee-fa14229aeeae
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3339457158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.3339457158 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_shake_128.2609503952
Short name	T408
Test name
Test status
Simulation time	461935353348 ps
CPU time	5381.95 seconds
Started	Jun 04 02:24:55 PM PDT 24
Finished	Jun 04 03:54:38 PM PDT 24
Peak memory	651932 kb
Host	smart-0279b5c5-924f-47d4-98f1-38f19491900b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2609503952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.2609503952 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_shake_256.752768062
Short name	T897
Test name
Test status
Simulation time	61473004067 ps
CPU time	4640.23 seconds
Started	Jun 04 02:24:56 PM PDT 24
Finished	Jun 04 03:42:18 PM PDT 24
Peak memory	575896 kb
Host	smart-fb43f251-a357-4f76-9579-36bd77e8b91b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=752768062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.752768062 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/12.kmac_alert_test.3483579619
Short name	T577
Test name
Test status
Simulation time	24674247 ps
CPU time	0.81 seconds
Started	Jun 04 02:25:23 PM PDT 24
Finished	Jun 04 02:25:24 PM PDT 24
Peak memory	218940 kb
Host	smart-9314d64d-b385-4a1d-a696-8a950d2f054b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483579619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.3483579619 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_alert_test/latest

Test location	/workspace/coverage/default/12.kmac_app.2177844019
Short name	T705
Test name
Test status
Simulation time	23210252152 ps
CPU time	326.2 seconds
Started	Jun 04 02:25:16 PM PDT 24
Finished	Jun 04 02:30:43 PM PDT 24
Peak memory	252604 kb
Host	smart-08e3ffef-c272-4a40-8f35-4079da26a1f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2177844019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.2177844019 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_app/latest

Test location	/workspace/coverage/default/12.kmac_burst_write.2256186346
Short name	T277
Test name
Test status
Simulation time	53055422064 ps
CPU time	922.79 seconds
Started	Jun 04 02:25:09 PM PDT 24
Finished	Jun 04 02:40:32 PM PDT 24
Peak memory	238320 kb
Host	smart-dd237cc0-45fb-4e2b-a0cc-96a27c108171
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2256186346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.2256186346 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_burst_write/latest

Test location	/workspace/coverage/default/12.kmac_edn_timeout_error.4216538407
Short name	T549
Test name
Test status
Simulation time	20630417 ps
CPU time	0.82 seconds
Started	Jun 04 02:25:19 PM PDT 24
Finished	Jun 04 02:25:20 PM PDT 24
Peak memory	222316 kb
Host	smart-7a3dbf9e-fc95-4352-99fb-0f80b4a6ed39
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4216538407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.4216538407 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/12.kmac_entropy_mode_error.1771649700
Short name	T74
Test name
Test status
Simulation time	35276846 ps
CPU time	1.07 seconds
Started	Jun 04 02:25:17 PM PDT 24
Finished	Jun 04 02:25:18 PM PDT 24
Peak memory	222120 kb
Host	smart-37a09174-40bf-4ae0-974f-391ba5ab9f7a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1771649700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.1771649700 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/12.kmac_entropy_refresh.1168808632
Short name	T499
Test name
Test status
Simulation time	17174457580 ps
CPU time	346.39 seconds
Started	Jun 04 02:25:16 PM PDT 24
Finished	Jun 04 02:31:03 PM PDT 24
Peak memory	251788 kb
Host	smart-0c91e6e4-9aba-4c09-8eed-65c6952b9119
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1168808632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.1168808632 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/12.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/12.kmac_error.3160764405
Short name	T502
Test name
Test status
Simulation time	91990328542 ps
CPU time	460.92 seconds
Started	Jun 04 02:25:19 PM PDT 24
Finished	Jun 04 02:33:01 PM PDT 24
Peak memory	266788 kb
Host	smart-cf2d08c8-953c-4c2b-8cfc-8d8c68b379a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3160764405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.3160764405 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_error/latest

Test location	/workspace/coverage/default/12.kmac_key_error.3024171989
Short name	T858
Test name
Test status
Simulation time	3875069885 ps
CPU time	7.32 seconds
Started	Jun 04 02:25:16 PM PDT 24
Finished	Jun 04 02:25:24 PM PDT 24
Peak memory	225192 kb
Host	smart-1497c7da-402a-446f-95dd-24faa005c1f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3024171989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3024171989 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_key_error/latest

Test location	/workspace/coverage/default/12.kmac_lc_escalation.2321847238
Short name	T1080
Test name
Test status
Simulation time	133784822 ps
CPU time	1.34 seconds
Started	Jun 04 02:25:16 PM PDT 24
Finished	Jun 04 02:25:18 PM PDT 24
Peak memory	227280 kb
Host	smart-6f6ba646-70a7-45a8-b0c9-e64bb4842605
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2321847238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.2321847238 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/12.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/12.kmac_long_msg_and_output.3734004581
Short name	T308
Test name
Test status
Simulation time	364617160763 ps
CPU time	2648.73 seconds
Started	Jun 04 02:25:11 PM PDT 24
Finished	Jun 04 03:09:20 PM PDT 24
Peak memory	416964 kb
Host	smart-1f1aa76f-771c-4353-b275-593df0ff1281
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734004581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a nd_output.3734004581 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/12.kmac_sideload.3364238155
Short name	T491
Test name
Test status
Simulation time	25290387402 ps
CPU time	154.87 seconds
Started	Jun 04 02:25:09 PM PDT 24
Finished	Jun 04 02:27:45 PM PDT 24
Peak memory	243900 kb
Host	smart-8da95188-4e42-4bda-8708-255efcf8804d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364238155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.3364238155 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_sideload/latest

Test location	/workspace/coverage/default/12.kmac_smoke.343399442
Short name	T823
Test name
Test status
Simulation time	2798344406 ps
CPU time	59.2 seconds
Started	Jun 04 02:25:10 PM PDT 24
Finished	Jun 04 02:26:10 PM PDT 24
Peak memory	227524 kb
Host	smart-f63a1312-4812-43a0-ab9d-1a4e2cadc3c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=343399442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.343399442 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_smoke/latest

Test location	/workspace/coverage/default/12.kmac_stress_all.116905159
Short name	T1044
Test name
Test status
Simulation time	113610548521 ps
CPU time	1387.98 seconds
Started	Jun 04 02:25:16 PM PDT 24
Finished	Jun 04 02:48:25 PM PDT 24
Peak memory	361568 kb
Host	smart-7870a1e3-b647-42db-8c2e-5b535c678b6b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=116905159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.116905159 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_stress_all/latest

Test location	/workspace/coverage/default/12.kmac_stress_all_with_rand_reset.2786372989
Short name	T133
Test name
Test status
Simulation time	25730191890 ps
CPU time	412.81 seconds
Started	Jun 04 02:25:22 PM PDT 24
Finished	Jun 04 02:32:16 PM PDT 24
Peak memory	257436 kb
Host	smart-77c69b9d-f4c5-4dda-b422-c2b917bd75cd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2786372989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all_with_rand_reset.2786372989 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_kmac.1569231953
Short name	T82
Test name
Test status
Simulation time	267783918 ps
CPU time	7.2 seconds
Started	Jun 04 02:25:14 PM PDT 24
Finished	Jun 04 02:25:21 PM PDT 24
Peak memory	219236 kb
Host	smart-b9c84184-77db-4a37-af53-a3694f65d88e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569231953 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.kmac_test_vectors_kmac.1569231953 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_kmac_xof.623488457
Short name	T553
Test name
Test status
Simulation time	91415511 ps
CPU time	5.51 seconds
Started	Jun 04 02:25:15 PM PDT 24
Finished	Jun 04 02:25:21 PM PDT 24
Peak memory	219352 kb
Host	smart-fd11e676-7589-42bf-bfa1-a422a4d602a6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623488457 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 12.kmac_test_vectors_kmac_xof.623488457 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_224.996592614
Short name	T259
Test name
Test status
Simulation time	97414053940 ps
CPU time	2316.42 seconds
Started	Jun 04 02:25:09 PM PDT 24
Finished	Jun 04 03:03:46 PM PDT 24
Peak memory	399140 kb
Host	smart-c8d2985c-a4be-4293-a4f0-ca83e77d5d59
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=996592614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.996592614 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_256.8268686
Short name	T980
Test name
Test status
Simulation time	94237862212 ps
CPU time	2171.73 seconds
Started	Jun 04 02:25:09 PM PDT 24
Finished	Jun 04 03:01:21 PM PDT 24
Peak memory	394624 kb
Host	smart-172786c1-f844-44aa-af6b-d1f50643a783
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=8268686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.8268686 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_384.1461403350
Short name	T824
Test name
Test status
Simulation time	50925158473 ps
CPU time	1594.88 seconds
Started	Jun 04 02:25:10 PM PDT 24
Finished	Jun 04 02:51:46 PM PDT 24
Peak memory	344956 kb
Host	smart-c54cde02-75d2-46b9-be72-f7aaff330f0d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1461403350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.1461403350 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_512.228436092
Short name	T737
Test name
Test status
Simulation time	35098028308 ps
CPU time	1242.09 seconds
Started	Jun 04 02:25:11 PM PDT 24
Finished	Jun 04 02:45:53 PM PDT 24
Peak memory	304688 kb
Host	smart-9ce55b07-49de-486c-856a-284dee77b130
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=228436092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.228436092 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_shake_128.4276566996
Short name	T455
Test name
Test status
Simulation time	2566758643532 ps
CPU time	6238.3 seconds
Started	Jun 04 02:25:09 PM PDT 24
Finished	Jun 04 04:09:09 PM PDT 24
Peak memory	652224 kb
Host	smart-bab406d2-f302-4972-a811-eff7b2e2e86c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4276566996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.4276566996 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_shake_256.3103755861
Short name	T510
Test name
Test status
Simulation time	52988557267 ps
CPU time	4515.22 seconds
Started	Jun 04 02:25:09 PM PDT 24
Finished	Jun 04 03:40:26 PM PDT 24
Peak memory	556592 kb
Host	smart-2822cb08-0deb-4121-911f-bc22e1675005
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3103755861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.3103755861 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/13.kmac_alert_test.714009114
Short name	T923
Test name
Test status
Simulation time	17917397 ps
CPU time	0.85 seconds
Started	Jun 04 02:25:36 PM PDT 24
Finished	Jun 04 02:25:38 PM PDT 24
Peak memory	218768 kb
Host	smart-1ce31c84-0199-4c57-a3b2-f271e2250e90
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714009114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.714009114 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_alert_test/latest

Test location	/workspace/coverage/default/13.kmac_app.1293263067
Short name	T696
Test name
Test status
Simulation time	19871794000 ps
CPU time	234.07 seconds
Started	Jun 04 02:25:28 PM PDT 24
Finished	Jun 04 02:29:23 PM PDT 24
Peak memory	247232 kb
Host	smart-9d4000e7-7f82-48eb-b7f7-f5ca3932907e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1293263067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.1293263067 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_app/latest

Test location	/workspace/coverage/default/13.kmac_burst_write.284691418
Short name	T147
Test name
Test status
Simulation time	18760582583 ps
CPU time	681.28 seconds
Started	Jun 04 02:25:21 PM PDT 24
Finished	Jun 04 02:36:43 PM PDT 24
Peak memory	240884 kb
Host	smart-de162277-d628-4efd-b007-9c7a534289b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=284691418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.284691418 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_burst_write/latest

Test location	/workspace/coverage/default/13.kmac_edn_timeout_error.4024640264
Short name	T209
Test name
Test status
Simulation time	809716935 ps
CPU time	46.18 seconds
Started	Jun 04 02:25:31 PM PDT 24
Finished	Jun 04 02:26:17 PM PDT 24
Peak memory	229596 kb
Host	smart-6074aed5-f3fd-48d2-8e7f-e23434fed2cd
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4024640264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.4024640264 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/13.kmac_entropy_mode_error.1078670455
Short name	T2
Test name
Test status
Simulation time	534535579 ps
CPU time	42.63 seconds
Started	Jun 04 02:25:30 PM PDT 24
Finished	Jun 04 02:26:13 PM PDT 24
Peak memory	227212 kb
Host	smart-8ca1bac8-4dd8-447d-be30-d7c146f3ae42
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1078670455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.1078670455 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/13.kmac_entropy_refresh.1106108602
Short name	T880
Test name
Test status
Simulation time	137624203467 ps
CPU time	401.87 seconds
Started	Jun 04 02:25:29 PM PDT 24
Finished	Jun 04 02:32:12 PM PDT 24
Peak memory	250484 kb
Host	smart-c95c9f5a-1078-4c56-952a-dc54fe70b43e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1106108602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.1106108602 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/13.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/13.kmac_error.501122326
Short name	T59
Test name
Test status
Simulation time	1219225143 ps
CPU time	48.34 seconds
Started	Jun 04 02:25:31 PM PDT 24
Finished	Jun 04 02:26:20 PM PDT 24
Peak memory	243800 kb
Host	smart-55d87b9b-007f-4d50-aeec-f38d7ba4a637
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=501122326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.501122326 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_error/latest

Test location	/workspace/coverage/default/13.kmac_key_error.1980882361
Short name	T954
Test name
Test status
Simulation time	451916961 ps
CPU time	5.01 seconds
Started	Jun 04 02:25:32 PM PDT 24
Finished	Jun 04 02:25:38 PM PDT 24
Peak memory	223876 kb
Host	smart-52a32f0a-1d19-4a68-a70a-6634b0287481
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1980882361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.1980882361 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_key_error/latest

Test location	/workspace/coverage/default/13.kmac_long_msg_and_output.2383838805
Short name	T406
Test name
Test status
Simulation time	42369394750 ps
CPU time	1488.36 seconds
Started	Jun 04 02:25:22 PM PDT 24
Finished	Jun 04 02:50:10 PM PDT 24
Peak memory	343952 kb
Host	smart-18f4aa6c-51d1-440f-9155-98a2aebdbeb5
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383838805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a nd_output.2383838805 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/13.kmac_sideload.2051645576
Short name	T535
Test name
Test status
Simulation time	1519795237 ps
CPU time	43.34 seconds
Started	Jun 04 02:25:21 PM PDT 24
Finished	Jun 04 02:26:05 PM PDT 24
Peak memory	226336 kb
Host	smart-f6eafb82-5a6d-451e-af70-ec925c1cdce7
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051645576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.2051645576 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_sideload/latest

Test location	/workspace/coverage/default/13.kmac_smoke.307510586
Short name	T951
Test name
Test status
Simulation time	11415005792 ps
CPU time	61.88 seconds
Started	Jun 04 02:25:22 PM PDT 24
Finished	Jun 04 02:26:24 PM PDT 24
Peak memory	219380 kb
Host	smart-e52f86b5-93b5-4298-9648-58317974775e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=307510586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.307510586 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_smoke/latest

Test location	/workspace/coverage/default/13.kmac_stress_all.1113902294
Short name	T662
Test name
Test status
Simulation time	8454928568 ps
CPU time	789.12 seconds
Started	Jun 04 02:25:32 PM PDT 24
Finished	Jun 04 02:38:42 PM PDT 24
Peak memory	289852 kb
Host	smart-0f7bd907-1aa3-44fa-8c97-770b3918efdd
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1113902294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.1113902294 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_stress_all/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_kmac.402912500
Short name	T440
Test name
Test status
Simulation time	188181903 ps
CPU time	6.22 seconds
Started	Jun 04 02:25:31 PM PDT 24
Finished	Jun 04 02:25:38 PM PDT 24
Peak memory	220316 kb
Host	smart-246107d1-5fa5-4071-829d-338b9a57b2ab
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402912500 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 13.kmac_test_vectors_kmac.402912500 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_kmac_xof.2580049058
Short name	T685
Test name
Test status
Simulation time	191452145 ps
CPU time	5.84 seconds
Started	Jun 04 02:25:31 PM PDT 24
Finished	Jun 04 02:25:37 PM PDT 24
Peak memory	220264 kb
Host	smart-52e66fe3-fb5b-468e-a042-bada7a6f2e09
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580049058 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_kmac_xof.2580049058 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_224.433197314
Short name	T588
Test name
Test status
Simulation time	20664922942 ps
CPU time	1878.16 seconds
Started	Jun 04 02:25:22 PM PDT 24
Finished	Jun 04 02:56:41 PM PDT 24
Peak memory	392448 kb
Host	smart-74cbe431-0971-4716-be78-640f3c8a4c08
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=433197314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.433197314 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_256.4283130623
Short name	T317
Test name
Test status
Simulation time	80605977204 ps
CPU time	1938.45 seconds
Started	Jun 04 02:25:20 PM PDT 24
Finished	Jun 04 02:57:40 PM PDT 24
Peak memory	374076 kb
Host	smart-8cf87270-c978-4ebd-a2ae-158e0ee36117
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4283130623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.4283130623 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_384.2607267611
Short name	T605
Test name
Test status
Simulation time	16326772801 ps
CPU time	1463.03 seconds
Started	Jun 04 02:25:22 PM PDT 24
Finished	Jun 04 02:49:46 PM PDT 24
Peak memory	339136 kb
Host	smart-aec64809-2340-4cbf-8eae-45fcb548193e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2607267611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.2607267611 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_512.3602004763
Short name	T1002
Test name
Test status
Simulation time	353974172600 ps
CPU time	1423.43 seconds
Started	Jun 04 02:25:23 PM PDT 24
Finished	Jun 04 02:49:07 PM PDT 24
Peak memory	303676 kb
Host	smart-7e48bb3a-86d7-4f64-8649-758580bd1865
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3602004763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.3602004763 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_shake_128.2666801648
Short name	T955
Test name
Test status
Simulation time	197525303360 ps
CPU time	5660.06 seconds
Started	Jun 04 02:25:23 PM PDT 24
Finished	Jun 04 03:59:44 PM PDT 24
Peak memory	636120 kb
Host	smart-654b75fb-6ea3-463a-a303-76097942977d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2666801648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.2666801648 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_shake_256.2098049905
Short name	T959
Test name
Test status
Simulation time	151523372607 ps
CPU time	4583.96 seconds
Started	Jun 04 02:25:30 PM PDT 24
Finished	Jun 04 03:41:55 PM PDT 24
Peak memory	566584 kb
Host	smart-cbf671e5-711d-4898-bd76-544046e8e519
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2098049905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.2098049905 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/14.kmac_alert_test.4222048572
Short name	T868
Test name
Test status
Simulation time	47988669 ps
CPU time	0.82 seconds
Started	Jun 04 02:25:48 PM PDT 24
Finished	Jun 04 02:25:49 PM PDT 24
Peak memory	218932 kb
Host	smart-e70ada21-95a4-44d8-8720-fb872469072b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222048572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.4222048572 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_alert_test/latest

Test location	/workspace/coverage/default/14.kmac_app.2899666143
Short name	T764
Test name
Test status
Simulation time	3234943124 ps
CPU time	198.63 seconds
Started	Jun 04 02:25:43 PM PDT 24
Finished	Jun 04 02:29:02 PM PDT 24
Peak memory	242880 kb
Host	smart-f8cc9f13-d0fd-433a-b3fb-75b91c949ea7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2899666143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.2899666143 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_app/latest

Test location	/workspace/coverage/default/14.kmac_burst_write.1275935440
Short name	T740
Test name
Test status
Simulation time	1146947233 ps
CPU time	45.28 seconds
Started	Jun 04 02:25:35 PM PDT 24
Finished	Jun 04 02:26:21 PM PDT 24
Peak memory	220636 kb
Host	smart-342d9c55-689d-4147-abe8-d9647d49cbe4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1275935440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.1275935440 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_burst_write/latest

Test location	/workspace/coverage/default/14.kmac_edn_timeout_error.2206490907
Short name	T397
Test name
Test status
Simulation time	59866189 ps
CPU time	1.04 seconds
Started	Jun 04 02:25:44 PM PDT 24
Finished	Jun 04 02:25:46 PM PDT 24
Peak memory	223868 kb
Host	smart-30d6c0ad-cbda-448d-b9e3-151dd4d9f0db
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2206490907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.2206490907 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/14.kmac_entropy_mode_error.1904482591
Short name	T318
Test name
Test status
Simulation time	33049041 ps
CPU time	1.02 seconds
Started	Jun 04 02:25:45 PM PDT 24
Finished	Jun 04 02:25:46 PM PDT 24
Peak memory	222276 kb
Host	smart-4bc8c54d-5cd9-4275-aa12-3801e67af3e1
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1904482591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.1904482591 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/14.kmac_error.1321577278
Short name	T441
Test name
Test status
Simulation time	5348993716 ps
CPU time	447.33 seconds
Started	Jun 04 02:25:44 PM PDT 24
Finished	Jun 04 02:33:12 PM PDT 24
Peak memory	268360 kb
Host	smart-4ce9ddfc-97d6-4986-92a2-5bde6e73cef2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321577278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.1321577278 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_error/latest

Test location	/workspace/coverage/default/14.kmac_key_error.1364355755
Short name	T1069
Test name
Test status
Simulation time	916101012 ps
CPU time	7.02 seconds
Started	Jun 04 02:25:45 PM PDT 24
Finished	Jun 04 02:25:52 PM PDT 24
Peak memory	223476 kb
Host	smart-a3a81ca2-b9be-4e7f-878c-f5b99d56b4ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1364355755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.1364355755 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_key_error/latest

Test location	/workspace/coverage/default/14.kmac_lc_escalation.458242501
Short name	T47
Test name
Test status
Simulation time	164990178 ps
CPU time	1.44 seconds
Started	Jun 04 02:25:44 PM PDT 24
Finished	Jun 04 02:25:46 PM PDT 24
Peak memory	227352 kb
Host	smart-4d38e67e-4bcf-46d7-9c3a-c78e306510e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=458242501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.458242501 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/14.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/14.kmac_long_msg_and_output.1354285589
Short name	T805
Test name
Test status
Simulation time	353120705262 ps
CPU time	2809.25 seconds
Started	Jun 04 02:25:36 PM PDT 24
Finished	Jun 04 03:12:27 PM PDT 24
Peak memory	455548 kb
Host	smart-8f9d4343-775d-4aef-a3a6-f391a9b02ed4
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354285589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a nd_output.1354285589 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/14.kmac_sideload.2333773700
Short name	T244
Test name
Test status
Simulation time	7057811078 ps
CPU time	54.36 seconds
Started	Jun 04 02:25:37 PM PDT 24
Finished	Jun 04 02:26:32 PM PDT 24
Peak memory	229148 kb
Host	smart-fd15ced2-6e1a-448a-a2a8-ad5aa7a82f43
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333773700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.2333773700 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_sideload/latest

Test location	/workspace/coverage/default/14.kmac_smoke.561792289
Short name	T991
Test name
Test status
Simulation time	725724159 ps
CPU time	15.31 seconds
Started	Jun 04 02:25:36 PM PDT 24
Finished	Jun 04 02:25:52 PM PDT 24
Peak memory	224780 kb
Host	smart-9b223408-afe4-4cc8-bdc5-a0f51715603c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=561792289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.561792289 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_smoke/latest

Test location	/workspace/coverage/default/14.kmac_stress_all.248926497
Short name	T1078
Test name
Test status
Simulation time	2785016643 ps
CPU time	26.65 seconds
Started	Jun 04 02:25:44 PM PDT 24
Finished	Jun 04 02:26:11 PM PDT 24
Peak memory	238244 kb
Host	smart-4643dd35-36f4-49a6-af98-69f39e808573
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=248926497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.248926497 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_stress_all/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_kmac.2874015578
Short name	T606
Test name
Test status
Simulation time	225193818 ps
CPU time	5.93 seconds
Started	Jun 04 02:25:44 PM PDT 24
Finished	Jun 04 02:25:51 PM PDT 24
Peak memory	219280 kb
Host	smart-83ec4fff-4672-4535-a78a-75dbe240abbd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874015578 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.kmac_test_vectors_kmac.2874015578 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_kmac_xof.4100664526
Short name	T912
Test name
Test status
Simulation time	134666991 ps
CPU time	5.44 seconds
Started	Jun 04 02:25:43 PM PDT 24
Finished	Jun 04 02:25:49 PM PDT 24
Peak memory	219276 kb
Host	smart-93304992-6e81-4610-afc8-663341046845
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100664526 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_kmac_xof.4100664526 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_224.1995973320
Short name	T484
Test name
Test status
Simulation time	112732364261 ps
CPU time	2045.44 seconds
Started	Jun 04 02:25:36 PM PDT 24
Finished	Jun 04 02:59:42 PM PDT 24
Peak memory	395112 kb
Host	smart-8da3acda-3f06-47a9-96d6-683323dff7b8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1995973320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.1995973320 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_256.1520932911
Short name	T229
Test name
Test status
Simulation time	40520377563 ps
CPU time	1848.42 seconds
Started	Jun 04 02:25:44 PM PDT 24
Finished	Jun 04 02:56:33 PM PDT 24
Peak memory	385312 kb
Host	smart-ae1f4bcf-12aa-4a37-acb7-373759b4d458
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1520932911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.1520932911 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_384.2946575178
Short name	T961
Test name
Test status
Simulation time	16622958491 ps
CPU time	1646.53 seconds
Started	Jun 04 02:25:44 PM PDT 24
Finished	Jun 04 02:53:11 PM PDT 24
Peak memory	341436 kb
Host	smart-05526ec0-6ba8-452e-b45e-12ce22ff5a75
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2946575178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.2946575178 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_512.67023496
Short name	T550
Test name
Test status
Simulation time	57784417095 ps
CPU time	1300.2 seconds
Started	Jun 04 02:25:44 PM PDT 24
Finished	Jun 04 02:47:25 PM PDT 24
Peak memory	301216 kb
Host	smart-aeb9b954-807a-4a4c-8754-0b14ac6b456f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=67023496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.67023496 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_shake_128.2915454024
Short name	T313
Test name
Test status
Simulation time	1013490542436 ps
CPU time	6407.57 seconds
Started	Jun 04 02:25:44 PM PDT 24
Finished	Jun 04 04:12:33 PM PDT 24
Peak memory	660780 kb
Host	smart-91ec9bb0-9bf2-4066-a21b-782bca524105
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2915454024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.2915454024 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_shake_256.2838022342
Short name	T984
Test name
Test status
Simulation time	218142249766 ps
CPU time	5425.29 seconds
Started	Jun 04 02:25:43 PM PDT 24
Finished	Jun 04 03:56:09 PM PDT 24
Peak memory	571996 kb
Host	smart-348f6aed-5a36-42a8-9656-63fe4002a47c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2838022342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.2838022342 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/15.kmac_alert_test.1625046463
Short name	T1077
Test name
Test status
Simulation time	257489809 ps
CPU time	0.91 seconds
Started	Jun 04 02:26:10 PM PDT 24
Finished	Jun 04 02:26:12 PM PDT 24
Peak memory	218916 kb
Host	smart-97586483-c634-48fa-b99c-38dafbde050b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625046463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.1625046463 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_alert_test/latest

Test location	/workspace/coverage/default/15.kmac_app.733436813
Short name	T698
Test name
Test status
Simulation time	4759168886 ps
CPU time	318.76 seconds
Started	Jun 04 02:26:03 PM PDT 24
Finished	Jun 04 02:31:22 PM PDT 24
Peak memory	251472 kb
Host	smart-2323e06e-ff6d-47d4-a84a-68578f24c657
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=733436813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.733436813 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_app/latest

Test location	/workspace/coverage/default/15.kmac_burst_write.998357067
Short name	T563
Test name
Test status
Simulation time	27378628834 ps
CPU time	938.37 seconds
Started	Jun 04 02:25:58 PM PDT 24
Finished	Jun 04 02:41:37 PM PDT 24
Peak memory	241476 kb
Host	smart-8b8cea07-0cca-46fc-b9ef-056c78e5803c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=998357067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.998357067 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_burst_write/latest

Test location	/workspace/coverage/default/15.kmac_edn_timeout_error.1971911051
Short name	T507
Test name
Test status
Simulation time	4393728501 ps
CPU time	55.39 seconds
Started	Jun 04 02:26:05 PM PDT 24
Finished	Jun 04 02:27:01 PM PDT 24
Peak memory	229388 kb
Host	smart-489f9217-c67f-477e-bd82-7e84da345ccb
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1971911051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1971911051 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/15.kmac_entropy_mode_error.3035344438
Short name	T413
Test name
Test status
Simulation time	18759194 ps
CPU time	1.07 seconds
Started	Jun 04 02:26:04 PM PDT 24
Finished	Jun 04 02:26:06 PM PDT 24
Peak memory	222228 kb
Host	smart-3054e929-2253-4e95-b6b7-c8775254cd21
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3035344438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.3035344438 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/15.kmac_entropy_refresh.4287738619
Short name	T102
Test name
Test status
Simulation time	29720737897 ps
CPU time	332.58 seconds
Started	Jun 04 02:26:03 PM PDT 24
Finished	Jun 04 02:31:36 PM PDT 24
Peak memory	250584 kb
Host	smart-9013bffe-f3b8-4831-aec6-de0dc8bc28bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4287738619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.4287738619 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/15.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/15.kmac_error.2010842823
Short name	T450
Test name
Test status
Simulation time	41503383629 ps
CPU time	332.06 seconds
Started	Jun 04 02:26:03 PM PDT 24
Finished	Jun 04 02:31:36 PM PDT 24
Peak memory	260260 kb
Host	smart-41048c78-5359-485c-a938-b5a3cbf497a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2010842823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.2010842823 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_error/latest

Test location	/workspace/coverage/default/15.kmac_key_error.4061920124
Short name	T448
Test name
Test status
Simulation time	1887920690 ps
CPU time	13.32 seconds
Started	Jun 04 02:26:03 PM PDT 24
Finished	Jun 04 02:26:17 PM PDT 24
Peak memory	225440 kb
Host	smart-2e8d98e4-ab40-4be2-a4d2-069083823970
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4061920124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.4061920124 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_key_error/latest

Test location	/workspace/coverage/default/15.kmac_lc_escalation.2042473143
Short name	T782
Test name
Test status
Simulation time	206802864 ps
CPU time	1.37 seconds
Started	Jun 04 02:26:09 PM PDT 24
Finished	Jun 04 02:26:11 PM PDT 24
Peak memory	226972 kb
Host	smart-3d4ae303-29e0-418a-b70a-34bf113b1d55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2042473143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.2042473143 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/15.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/15.kmac_long_msg_and_output.1089597969
Short name	T1017
Test name
Test status
Simulation time	199829789240 ps
CPU time	2576.11 seconds
Started	Jun 04 02:25:50 PM PDT 24
Finished	Jun 04 03:08:47 PM PDT 24
Peak memory	423604 kb
Host	smart-f684bc17-3904-4f53-b336-c8a9e5b2dcc3
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089597969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a nd_output.1089597969 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/15.kmac_sideload.1932105126
Short name	T966
Test name
Test status
Simulation time	9270051742 ps
CPU time	242.68 seconds
Started	Jun 04 02:25:49 PM PDT 24
Finished	Jun 04 02:29:53 PM PDT 24
Peak memory	243856 kb
Host	smart-74173814-1e7b-4b9f-8242-5d05f6e99012
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932105126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.1932105126 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_sideload/latest

Test location	/workspace/coverage/default/15.kmac_smoke.2776146311
Short name	T473
Test name
Test status
Simulation time	5107704578 ps
CPU time	26.08 seconds
Started	Jun 04 02:25:52 PM PDT 24
Finished	Jun 04 02:26:19 PM PDT 24
Peak memory	227076 kb
Host	smart-2cdf995b-3c7a-401d-852f-cd9f9ca9b55c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2776146311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.2776146311 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_smoke/latest

Test location	/workspace/coverage/default/15.kmac_stress_all.3170732637
Short name	T341
Test name
Test status
Simulation time	65078781823 ps
CPU time	476.55 seconds
Started	Jun 04 02:26:11 PM PDT 24
Finished	Jun 04 02:34:08 PM PDT 24
Peak memory	270544 kb
Host	smart-4c211d80-3aed-4bea-bb03-323849a2cc10
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3170732637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.3170732637 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_stress_all/latest

Test location	/workspace/coverage/default/15.kmac_stress_all_with_rand_reset.1748812679
Short name	T688
Test name
Test status
Simulation time	72236389115 ps
CPU time	380.92 seconds
Started	Jun 04 02:26:10 PM PDT 24
Finished	Jun 04 02:32:31 PM PDT 24
Peak memory	259820 kb
Host	smart-dd451546-0ce8-46fa-ba1b-1bf580d02552
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1748812679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all_with_rand_reset.1748812679 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_kmac.495584775
Short name	T800
Test name
Test status
Simulation time	238700383 ps
CPU time	5.86 seconds
Started	Jun 04 02:26:05 PM PDT 24
Finished	Jun 04 02:26:12 PM PDT 24
Peak memory	219356 kb
Host	smart-08b9382f-1928-40c1-ac2a-c994ff2fbb7b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495584775 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 15.kmac_test_vectors_kmac.495584775 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_kmac_xof.3157044055
Short name	T403
Test name
Test status
Simulation time	91938062 ps
CPU time	5.34 seconds
Started	Jun 04 02:26:03 PM PDT 24
Finished	Jun 04 02:26:09 PM PDT 24
Peak memory	219332 kb
Host	smart-6f34303e-4e77-4944-80b4-4181efd89d86
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157044055 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_kmac_xof.3157044055 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_224.2533237666
Short name	T988
Test name
Test status
Simulation time	66154702595 ps
CPU time	1969.66 seconds
Started	Jun 04 02:25:57 PM PDT 24
Finished	Jun 04 02:58:48 PM PDT 24
Peak memory	389328 kb
Host	smart-4b1b8794-31b5-426c-98b1-eece9cc6d8d6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2533237666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.2533237666 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_256.524939995
Short name	T377
Test name
Test status
Simulation time	96281639455 ps
CPU time	1959.05 seconds
Started	Jun 04 02:25:59 PM PDT 24
Finished	Jun 04 02:58:39 PM PDT 24
Peak memory	385424 kb
Host	smart-576a33a5-aac3-4ba4-9e3b-f55ba6764fcc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=524939995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.524939995 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_384.450410720
Short name	T371
Test name
Test status
Simulation time	784771220042 ps
CPU time	1829.61 seconds
Started	Jun 04 02:25:55 PM PDT 24
Finished	Jun 04 02:56:25 PM PDT 24
Peak memory	338720 kb
Host	smart-96d5226e-5cd2-4dfc-ba94-3efa00e5012a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=450410720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.450410720 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_512.2511875865
Short name	T866
Test name
Test status
Simulation time	11449568290 ps
CPU time	1208.72 seconds
Started	Jun 04 02:25:56 PM PDT 24
Finished	Jun 04 02:46:06 PM PDT 24
Peak memory	299824 kb
Host	smart-ab088567-79c6-414a-9232-e50e4e40851a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2511875865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.2511875865 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_shake_128.2238470362
Short name	T206
Test name
Test status
Simulation time	63644305463 ps
CPU time	5659.29 seconds
Started	Jun 04 02:25:55 PM PDT 24
Finished	Jun 04 04:00:16 PM PDT 24
Peak memory	676372 kb
Host	smart-f74409ee-9e42-48eb-8603-cf9b4bc5282f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2238470362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.2238470362 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_shake_256.1588866461
Short name	T635
Test name
Test status
Simulation time	562950793843 ps
CPU time	4941.97 seconds
Started	Jun 04 02:25:57 PM PDT 24
Finished	Jun 04 03:48:20 PM PDT 24
Peak memory	570076 kb
Host	smart-f7ba4ba2-5a70-466c-b200-09c6ffad6e0b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1588866461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.1588866461 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/16.kmac_alert_test.4235955200
Short name	T411
Test name
Test status
Simulation time	25544555 ps
CPU time	0.82 seconds
Started	Jun 04 02:26:32 PM PDT 24
Finished	Jun 04 02:26:33 PM PDT 24
Peak memory	218912 kb
Host	smart-76f799ae-1d93-4627-adb9-a6747a7e50f0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235955200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.4235955200 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_alert_test/latest

Test location	/workspace/coverage/default/16.kmac_app.2942253336
Short name	T832
Test name
Test status
Simulation time	18909403804 ps
CPU time	194.41 seconds
Started	Jun 04 02:26:17 PM PDT 24
Finished	Jun 04 02:29:32 PM PDT 24
Peak memory	242992 kb
Host	smart-058b640c-6dae-4642-b192-b51378177453
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2942253336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2942253336 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_app/latest

Test location	/workspace/coverage/default/16.kmac_burst_write.4134845954
Short name	T562
Test name
Test status
Simulation time	4128872428 ps
CPU time	414.11 seconds
Started	Jun 04 02:26:11 PM PDT 24
Finished	Jun 04 02:33:06 PM PDT 24
Peak memory	243844 kb
Host	smart-0ee3da01-72e0-4e64-8bfe-33b7e880e246
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134845954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.4134845954 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_burst_write/latest

Test location	/workspace/coverage/default/16.kmac_edn_timeout_error.3916201089
Short name	T212
Test name
Test status
Simulation time	86963418 ps
CPU time	6.68 seconds
Started	Jun 04 02:26:33 PM PDT 24
Finished	Jun 04 02:26:40 PM PDT 24
Peak memory	227732 kb
Host	smart-c22d2b13-3853-46f8-bf7a-361b8f7013b0
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3916201089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3916201089 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/16.kmac_entropy_mode_error.1744844421
Short name	T330
Test name
Test status
Simulation time	53320764 ps
CPU time	1.03 seconds
Started	Jun 04 02:26:34 PM PDT 24
Finished	Jun 04 02:26:36 PM PDT 24
Peak memory	218844 kb
Host	smart-ca9772f6-28b3-4fee-bbdf-de5cf698d1ae
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1744844421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.1744844421 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/16.kmac_entropy_refresh.1308351470
Short name	T952
Test name
Test status
Simulation time	3101756821 ps
CPU time	60.47 seconds
Started	Jun 04 02:26:17 PM PDT 24
Finished	Jun 04 02:27:18 PM PDT 24
Peak memory	237556 kb
Host	smart-215a48bb-3712-4bcd-abe3-470ecd9500f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1308351470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.1308351470 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/16.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/16.kmac_error.2085614851
Short name	T461
Test name
Test status
Simulation time	60766379352 ps
CPU time	382.09 seconds
Started	Jun 04 02:26:17 PM PDT 24
Finished	Jun 04 02:32:39 PM PDT 24
Peak memory	260236 kb
Host	smart-23bd91fb-76f4-453e-8d43-70947c00807d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2085614851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.2085614851 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_error/latest

Test location	/workspace/coverage/default/16.kmac_key_error.2665570747
Short name	T561
Test name
Test status
Simulation time	536393203 ps
CPU time	2.65 seconds
Started	Jun 04 02:26:15 PM PDT 24
Finished	Jun 04 02:26:19 PM PDT 24
Peak memory	223220 kb
Host	smart-c6352a8a-ffe1-486d-a038-38c8c539e62a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2665570747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.2665570747 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_key_error/latest

Test location	/workspace/coverage/default/16.kmac_long_msg_and_output.2248986391
Short name	T236
Test name
Test status
Simulation time	63680950129 ps
CPU time	2763.72 seconds
Started	Jun 04 02:26:10 PM PDT 24
Finished	Jun 04 03:12:14 PM PDT 24
Peak memory	483356 kb
Host	smart-6ef739af-6aef-4ba3-a4ff-d9888cf28f39
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248986391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a nd_output.2248986391 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/16.kmac_sideload.790610387
Short name	T319
Test name
Test status
Simulation time	2046251927 ps
CPU time	67.63 seconds
Started	Jun 04 02:26:11 PM PDT 24
Finished	Jun 04 02:27:20 PM PDT 24
Peak memory	238268 kb
Host	smart-192fa445-44f6-4ea6-8a34-e493e28e765c
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790610387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.790610387 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_sideload/latest

Test location	/workspace/coverage/default/16.kmac_smoke.962657685
Short name	T675
Test name
Test status
Simulation time	1988605786 ps
CPU time	41.17 seconds
Started	Jun 04 02:26:09 PM PDT 24
Finished	Jun 04 02:26:51 PM PDT 24
Peak memory	227272 kb
Host	smart-4e97ad4a-d955-4ac0-9318-fd8031eb39ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=962657685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.962657685 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_smoke/latest

Test location	/workspace/coverage/default/16.kmac_stress_all.504781713
Short name	T595
Test name
Test status
Simulation time	116311260086 ps
CPU time	1009.05 seconds
Started	Jun 04 02:26:23 PM PDT 24
Finished	Jun 04 02:43:12 PM PDT 24
Peak memory	335292 kb
Host	smart-6b44ad1b-18c3-4490-aa4e-2fe6ab744d04
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=504781713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.504781713 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_stress_all/latest

Test location	/workspace/coverage/default/16.kmac_stress_all_with_rand_reset.2585305157
Short name	T755
Test name
Test status
Simulation time	362624822559 ps
CPU time	1187.48 seconds
Started	Jun 04 02:26:23 PM PDT 24
Finished	Jun 04 02:46:11 PM PDT 24
Peak memory	323108 kb
Host	smart-ace9b2d4-a359-4ef2-8891-a9b04d084053
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2585305157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all_with_rand_reset.2585305157 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_kmac.1337659404
Short name	T488
Test name
Test status
Simulation time	420032489 ps
CPU time	6.15 seconds
Started	Jun 04 02:26:18 PM PDT 24
Finished	Jun 04 02:26:25 PM PDT 24
Peak memory	219300 kb
Host	smart-485570ab-a70c-499f-8c6e-33ed259a9135
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337659404 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.kmac_test_vectors_kmac.1337659404 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_kmac_xof.2436926830
Short name	T628
Test name
Test status
Simulation time	225280500 ps
CPU time	6.89 seconds
Started	Jun 04 02:26:15 PM PDT 24
Finished	Jun 04 02:26:23 PM PDT 24
Peak memory	219296 kb
Host	smart-3eaa1217-3fc1-4398-93ba-a77d6e6cd581
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436926830 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_kmac_xof.2436926830 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_224.3561617570
Short name	T918
Test name
Test status
Simulation time	40252403375 ps
CPU time	1920.58 seconds
Started	Jun 04 02:26:11 PM PDT 24
Finished	Jun 04 02:58:12 PM PDT 24
Peak memory	407796 kb
Host	smart-fa081654-d923-4685-b82e-14350f3ed469
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3561617570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.3561617570 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_256.1547372581
Short name	T603
Test name
Test status
Simulation time	95631323599 ps
CPU time	2340.82 seconds
Started	Jun 04 02:26:17 PM PDT 24
Finished	Jun 04 03:05:18 PM PDT 24
Peak memory	383680 kb
Host	smart-2f5a5565-ce5d-47cb-9ca8-f5d2c8e48896
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1547372581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.1547372581 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_384.3005548499
Short name	T799
Test name
Test status
Simulation time	34457606802 ps
CPU time	1646.47 seconds
Started	Jun 04 02:26:17 PM PDT 24
Finished	Jun 04 02:53:44 PM PDT 24
Peak memory	348128 kb
Host	smart-3a723694-4cc0-4f3b-8535-9ac4d771d33a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3005548499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.3005548499 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_512.3187308273
Short name	T36
Test name
Test status
Simulation time	45049359946 ps
CPU time	1106.41 seconds
Started	Jun 04 02:26:16 PM PDT 24
Finished	Jun 04 02:44:43 PM PDT 24
Peak memory	301148 kb
Host	smart-e882431a-a72b-4ee3-b24c-0413009c426b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3187308273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.3187308273 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_shake_128.2347913360
Short name	T526
Test name
Test status
Simulation time	65458547139 ps
CPU time	5290.47 seconds
Started	Jun 04 02:26:16 PM PDT 24
Finished	Jun 04 03:54:27 PM PDT 24
Peak memory	652828 kb
Host	smart-1cf7c84e-82fc-4c35-9e61-b572b2ee0aa8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2347913360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.2347913360 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_shake_256.3075104345
Short name	T240
Test name
Test status
Simulation time	888727854422 ps
CPU time	5738.16 seconds
Started	Jun 04 02:26:22 PM PDT 24
Finished	Jun 04 04:02:02 PM PDT 24
Peak memory	584096 kb
Host	smart-ed0bc622-9de5-46da-bd71-12ac72bf6931
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3075104345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.3075104345 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/17.kmac_alert_test.2571141223
Short name	T251
Test name
Test status
Simulation time	140764526 ps
CPU time	0.8 seconds
Started	Jun 04 02:26:42 PM PDT 24
Finished	Jun 04 02:26:43 PM PDT 24
Peak memory	218928 kb
Host	smart-d213b37b-6d69-402c-859e-00734febefe5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571141223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.2571141223 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_alert_test/latest

Test location	/workspace/coverage/default/17.kmac_app.2194445545
Short name	T232
Test name
Test status
Simulation time	1979824635 ps
CPU time	22.77 seconds
Started	Jun 04 02:26:36 PM PDT 24
Finished	Jun 04 02:27:00 PM PDT 24
Peak memory	227344 kb
Host	smart-141e26a2-2587-4cf7-a8e6-f9c6c33f8648
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2194445545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2194445545 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_app/latest

Test location	/workspace/coverage/default/17.kmac_burst_write.1889229412
Short name	T537
Test name
Test status
Simulation time	8115077546 ps
CPU time	197.7 seconds
Started	Jun 04 02:26:36 PM PDT 24
Finished	Jun 04 02:29:54 PM PDT 24
Peak memory	228712 kb
Host	smart-35f4a60c-48c0-433e-a2ea-389b2b916379
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1889229412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.1889229412 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_burst_write/latest

Test location	/workspace/coverage/default/17.kmac_edn_timeout_error.266419923
Short name	T65
Test name
Test status
Simulation time	124294228 ps
CPU time	1.11 seconds
Started	Jun 04 02:26:34 PM PDT 24
Finished	Jun 04 02:26:36 PM PDT 24
Peak memory	223720 kb
Host	smart-395621aa-357d-40dc-b276-43fd6ae53e7e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=266419923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.266419923 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/17.kmac_entropy_mode_error.3238696613
Short name	T73
Test name
Test status
Simulation time	22859858 ps
CPU time	1.08 seconds
Started	Jun 04 02:26:36 PM PDT 24
Finished	Jun 04 02:26:37 PM PDT 24
Peak memory	222288 kb
Host	smart-99c6ceca-e615-47bf-b395-ac3bd4c6cbcf
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3238696613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.3238696613 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/17.kmac_entropy_refresh.830361461
Short name	T670
Test name
Test status
Simulation time	2227745270 ps
CPU time	84.78 seconds
Started	Jun 04 02:26:36 PM PDT 24
Finished	Jun 04 02:28:01 PM PDT 24
Peak memory	235696 kb
Host	smart-746d9f2b-e01e-4126-bcc3-58665b9fe6c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=830361461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.830361461 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/17.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/17.kmac_error.2598055503
Short name	T847
Test name
Test status
Simulation time	21402008220 ps
CPU time	156.13 seconds
Started	Jun 04 02:26:29 PM PDT 24
Finished	Jun 04 02:29:06 PM PDT 24
Peak memory	245012 kb
Host	smart-79156c73-4e77-4ea2-a135-49448a2d686c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2598055503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.2598055503 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_error/latest

Test location	/workspace/coverage/default/17.kmac_key_error.1895187760
Short name	T767
Test name
Test status
Simulation time	325167196 ps
CPU time	3.27 seconds
Started	Jun 04 02:26:34 PM PDT 24
Finished	Jun 04 02:26:38 PM PDT 24
Peak memory	223220 kb
Host	smart-32f0f371-5629-450e-9710-7ca57312f3c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1895187760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.1895187760 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_key_error/latest

Test location	/workspace/coverage/default/17.kmac_lc_escalation.1014031053
Short name	T81
Test name
Test status
Simulation time	32248032 ps
CPU time	1.32 seconds
Started	Jun 04 02:26:40 PM PDT 24
Finished	Jun 04 02:26:41 PM PDT 24
Peak memory	227312 kb
Host	smart-9e81fa14-0c8e-49ff-ba01-f10b6bf04c6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1014031053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.1014031053 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/17.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/17.kmac_long_msg_and_output.3285061713
Short name	T1050
Test name
Test status
Simulation time	439038793211 ps
CPU time	2805.56 seconds
Started	Jun 04 02:26:22 PM PDT 24
Finished	Jun 04 03:13:08 PM PDT 24
Peak memory	450996 kb
Host	smart-7a1bc278-b991-4bd9-9e2e-f4bd34b99014
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285061713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a nd_output.3285061713 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/17.kmac_sideload.776581404
Short name	T937
Test name
Test status
Simulation time	5112604106 ps
CPU time	157.12 seconds
Started	Jun 04 02:26:23 PM PDT 24
Finished	Jun 04 02:29:00 PM PDT 24
Peak memory	238796 kb
Host	smart-a839737c-5890-4d6f-9ec4-0e87ec5dd2a8
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776581404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.776581404 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_sideload/latest

Test location	/workspace/coverage/default/17.kmac_smoke.3956728761
Short name	T576
Test name
Test status
Simulation time	4645245902 ps
CPU time	22.8 seconds
Started	Jun 04 02:26:22 PM PDT 24
Finished	Jun 04 02:26:45 PM PDT 24
Peak memory	223400 kb
Host	smart-7baf3a0b-eaf1-4493-879a-e16aca1144a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3956728761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.3956728761 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_smoke/latest

Test location	/workspace/coverage/default/17.kmac_stress_all.69074193
Short name	T53
Test name
Test status
Simulation time	8325801532 ps
CPU time	260.81 seconds
Started	Jun 04 02:26:47 PM PDT 24
Finished	Jun 04 02:31:08 PM PDT 24
Peak memory	285192 kb
Host	smart-a2595489-9758-415b-9ef0-b0b53db9fa90
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=69074193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.69074193 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_stress_all/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_kmac.3321450432
Short name	T879
Test name
Test status
Simulation time	480556351 ps
CPU time	6.26 seconds
Started	Jun 04 02:26:37 PM PDT 24
Finished	Jun 04 02:26:43 PM PDT 24
Peak memory	219276 kb
Host	smart-a1484c8d-722c-40d4-b857-ea19263c8f62
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321450432 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.kmac_test_vectors_kmac.3321450432 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_kmac_xof.1803746436
Short name	T753
Test name
Test status
Simulation time	204725492 ps
CPU time	6.16 seconds
Started	Jun 04 02:26:36 PM PDT 24
Finished	Jun 04 02:26:43 PM PDT 24
Peak memory	219284 kb
Host	smart-4ebcea0a-cd3e-4c70-a586-78e58b521108
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803746436 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_kmac_xof.1803746436 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_224.2930673074
Short name	T512
Test name
Test status
Simulation time	819210763519 ps
CPU time	2643.84 seconds
Started	Jun 04 02:26:29 PM PDT 24
Finished	Jun 04 03:10:33 PM PDT 24
Peak memory	402024 kb
Host	smart-e03049f0-c5ec-4630-b890-705e9abce897
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2930673074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.2930673074 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_256.1835108168
Short name	T989
Test name
Test status
Simulation time	19014518359 ps
CPU time	1803.25 seconds
Started	Jun 04 02:26:29 PM PDT 24
Finished	Jun 04 02:56:33 PM PDT 24
Peak memory	382892 kb
Host	smart-fb064e03-2059-4bba-81f2-b013ca05cd4b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1835108168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.1835108168 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_384.1922655009
Short name	T630
Test name
Test status
Simulation time	73964221541 ps
CPU time	1511.25 seconds
Started	Jun 04 02:26:29 PM PDT 24
Finished	Jun 04 02:51:40 PM PDT 24
Peak memory	346504 kb
Host	smart-14b222ae-83ae-4ee9-bf9f-0edda3767353
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1922655009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.1922655009 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_512.772128899
Short name	T766
Test name
Test status
Simulation time	70013211623 ps
CPU time	1274.59 seconds
Started	Jun 04 02:26:29 PM PDT 24
Finished	Jun 04 02:47:45 PM PDT 24
Peak memory	307088 kb
Host	smart-130a5b3a-485a-4589-ae9e-8727e45eecb8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=772128899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.772128899 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_shake_128.691101657
Short name	T205
Test name
Test status
Simulation time	150173163340 ps
CPU time	5685.68 seconds
Started	Jun 04 02:26:29 PM PDT 24
Finished	Jun 04 04:01:16 PM PDT 24
Peak memory	662224 kb
Host	smart-60191a41-46e8-4944-ae0f-915bbf2aa82e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=691101657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.691101657 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_shake_256.658415769
Short name	T346
Test name
Test status
Simulation time	194128673645 ps
CPU time	5140.31 seconds
Started	Jun 04 02:26:30 PM PDT 24
Finished	Jun 04 03:52:12 PM PDT 24
Peak memory	571660 kb
Host	smart-ba4de7e3-4d91-47c4-a877-1b2cc2d91ae8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=658415769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.658415769 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/18.kmac_alert_test.704981358
Short name	T885
Test name
Test status
Simulation time	14771852 ps
CPU time	0.81 seconds
Started	Jun 04 02:26:58 PM PDT 24
Finished	Jun 04 02:26:59 PM PDT 24
Peak memory	218940 kb
Host	smart-40bb8f48-c253-494c-8c8a-73fd14b68b1c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704981358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.704981358 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_alert_test/latest

Test location	/workspace/coverage/default/18.kmac_app.2416539368
Short name	T213
Test name
Test status
Simulation time	9323740699 ps
CPU time	136.44 seconds
Started	Jun 04 02:26:57 PM PDT 24
Finished	Jun 04 02:29:14 PM PDT 24
Peak memory	237700 kb
Host	smart-8825332e-72c5-4b54-8d9b-10aeb956fca6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2416539368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.2416539368 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_app/latest

Test location	/workspace/coverage/default/18.kmac_burst_write.1975210886
Short name	T409
Test name
Test status
Simulation time	4930977088 ps
CPU time	621.1 seconds
Started	Jun 04 02:26:48 PM PDT 24
Finished	Jun 04 02:37:10 PM PDT 24
Peak memory	232880 kb
Host	smart-80c14dc9-08fa-4cb2-b7e7-3bff6ccf44de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1975210886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.1975210886 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_burst_write/latest

Test location	/workspace/coverage/default/18.kmac_edn_timeout_error.291831873
Short name	T986
Test name
Test status
Simulation time	59917543 ps
CPU time	1.11 seconds
Started	Jun 04 02:26:55 PM PDT 24
Finished	Jun 04 02:26:57 PM PDT 24
Peak memory	223928 kb
Host	smart-a84909f9-3022-43c6-a071-e3cea70facaf
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=291831873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.291831873 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/18.kmac_entropy_mode_error.3705644842
Short name	T539
Test name
Test status
Simulation time	39405318 ps
CPU time	0.91 seconds
Started	Jun 04 02:26:55 PM PDT 24
Finished	Jun 04 02:26:57 PM PDT 24
Peak memory	221136 kb
Host	smart-6ebec6f9-0ae7-42a9-bc67-e5b50a486028
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3705644842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.3705644842 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/18.kmac_entropy_refresh.3245867200
Short name	T975
Test name
Test status
Simulation time	3518273731 ps
CPU time	57.09 seconds
Started	Jun 04 02:26:55 PM PDT 24
Finished	Jun 04 02:27:53 PM PDT 24
Peak memory	229604 kb
Host	smart-b8475c83-54f2-4838-b72b-ebda9fa877eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3245867200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3245867200 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/18.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/18.kmac_key_error.1103626846
Short name	T790
Test name
Test status
Simulation time	1017883171 ps
CPU time	7.5 seconds
Started	Jun 04 02:26:56 PM PDT 24
Finished	Jun 04 02:27:04 PM PDT 24
Peak memory	223992 kb
Host	smart-1a9878d6-7f87-4b3d-92ee-ce915ece7289
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1103626846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.1103626846 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_key_error/latest

Test location	/workspace/coverage/default/18.kmac_lc_escalation.105282694
Short name	T49
Test name
Test status
Simulation time	122640921 ps
CPU time	1.53 seconds
Started	Jun 04 02:26:57 PM PDT 24
Finished	Jun 04 02:26:59 PM PDT 24
Peak memory	227216 kb
Host	smart-161b8a2c-1cbc-44bf-88b5-fd9b12b67f7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105282694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.105282694 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/18.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/18.kmac_long_msg_and_output.2239053715
Short name	T876
Test name
Test status
Simulation time	87220927865 ps
CPU time	2379.2 seconds
Started	Jun 04 02:26:42 PM PDT 24
Finished	Jun 04 03:06:22 PM PDT 24
Peak memory	422568 kb
Host	smart-d2097009-00c3-4249-b6ab-86b6fd1c67c6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239053715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a nd_output.2239053715 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/18.kmac_sideload.2909318765
Short name	T1057
Test name
Test status
Simulation time	15576473493 ps
CPU time	282.5 seconds
Started	Jun 04 02:26:43 PM PDT 24
Finished	Jun 04 02:31:26 PM PDT 24
Peak memory	244708 kb
Host	smart-b763a681-9955-4911-a439-12adad7c66c4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909318765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2909318765 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_sideload/latest

Test location	/workspace/coverage/default/18.kmac_smoke.1017931661
Short name	T198
Test name
Test status
Simulation time	3584701214 ps
CPU time	32.3 seconds
Started	Jun 04 02:26:42 PM PDT 24
Finished	Jun 04 02:27:15 PM PDT 24
Peak memory	227376 kb
Host	smart-7c6eea88-950b-4f07-a750-75199a7f493e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1017931661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.1017931661 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_smoke/latest

Test location	/workspace/coverage/default/18.kmac_stress_all.3130609304
Short name	T1041
Test name
Test status
Simulation time	687928590632 ps
CPU time	1678.1 seconds
Started	Jun 04 02:26:57 PM PDT 24
Finished	Jun 04 02:54:56 PM PDT 24
Peak memory	355460 kb
Host	smart-77fc80bd-5c0a-41cd-bfea-7094fbb59b93
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3130609304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.3130609304 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_stress_all/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_kmac.3277334202
Short name	T751
Test name
Test status
Simulation time	217583702 ps
CPU time	6.17 seconds
Started	Jun 04 02:26:50 PM PDT 24
Finished	Jun 04 02:26:56 PM PDT 24
Peak memory	219288 kb
Host	smart-90b2d47e-5ab9-4552-80e1-53a43a4e56f6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277334202 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.kmac_test_vectors_kmac.3277334202 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_kmac_xof.3528660062
Short name	T713
Test name
Test status
Simulation time	348956630 ps
CPU time	6.01 seconds
Started	Jun 04 02:26:49 PM PDT 24
Finished	Jun 04 02:26:56 PM PDT 24
Peak memory	219272 kb
Host	smart-6287a0e1-ce85-448d-8e4d-7263a0835bf7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528660062 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_kmac_xof.3528660062 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_224.3725950441
Short name	T1070
Test name
Test status
Simulation time	85823933202 ps
CPU time	2337.85 seconds
Started	Jun 04 02:26:50 PM PDT 24
Finished	Jun 04 03:05:49 PM PDT 24
Peak memory	393444 kb
Host	smart-472c148d-54b9-4790-8c12-82278623829d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3725950441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.3725950441 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_256.148310373
Short name	T375
Test name
Test status
Simulation time	666175451750 ps
CPU time	2157.28 seconds
Started	Jun 04 02:26:50 PM PDT 24
Finished	Jun 04 03:02:48 PM PDT 24
Peak memory	377064 kb
Host	smart-4a1f2f92-698a-4695-9cd9-b9e9bdcea8d4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=148310373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.148310373 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_384.3178988347
Short name	T179
Test name
Test status
Simulation time	133372988804 ps
CPU time	1544.68 seconds
Started	Jun 04 02:26:49 PM PDT 24
Finished	Jun 04 02:52:34 PM PDT 24
Peak memory	336512 kb
Host	smart-19a7bced-8eab-4e52-a3e7-88b1ecd09ceb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3178988347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.3178988347 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_512.4201498696
Short name	T1037
Test name
Test status
Simulation time	11310830902 ps
CPU time	1046.35 seconds
Started	Jun 04 02:26:49 PM PDT 24
Finished	Jun 04 02:44:16 PM PDT 24
Peak memory	303872 kb
Host	smart-104ccc9f-bfaa-4fec-a8a9-493f8a7e9955
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4201498696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.4201498696 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_shake_128.3546193819
Short name	T844
Test name
Test status
Simulation time	259108468623 ps
CPU time	6152.26 seconds
Started	Jun 04 02:26:50 PM PDT 24
Finished	Jun 04 04:09:24 PM PDT 24
Peak memory	648356 kb
Host	smart-7d68c441-60be-4cf1-854b-f0ad6c5b1902
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3546193819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.3546193819 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_shake_256.3775758183
Short name	T663
Test name
Test status
Simulation time	602979114422 ps
CPU time	5176.45 seconds
Started	Jun 04 02:26:49 PM PDT 24
Finished	Jun 04 03:53:06 PM PDT 24
Peak memory	565736 kb
Host	smart-e60d92b4-b6ef-403e-97ce-660988592108
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3775758183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.3775758183 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/19.kmac_alert_test.104248906
Short name	T367
Test name
Test status
Simulation time	193084913 ps
CPU time	0.92 seconds
Started	Jun 04 02:27:16 PM PDT 24
Finished	Jun 04 02:27:17 PM PDT 24
Peak memory	218904 kb
Host	smart-01ca383c-e978-4636-b94f-fb61dd278485
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104248906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.104248906 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_alert_test/latest

Test location	/workspace/coverage/default/19.kmac_app.1792735269
Short name	T552
Test name
Test status
Simulation time	6300919742 ps
CPU time	363.21 seconds
Started	Jun 04 02:27:25 PM PDT 24
Finished	Jun 04 02:33:29 PM PDT 24
Peak memory	251796 kb
Host	smart-74da4e68-ea95-41f0-a109-02227d712853
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1792735269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.1792735269 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_app/latest

Test location	/workspace/coverage/default/19.kmac_burst_write.3445831994
Short name	T957
Test name
Test status
Simulation time	4247416345 ps
CPU time	400.26 seconds
Started	Jun 04 02:27:02 PM PDT 24
Finished	Jun 04 02:33:42 PM PDT 24
Peak memory	232272 kb
Host	smart-be8e4a9a-effa-4d94-b3b4-1232f2a01247
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3445831994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.3445831994 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_burst_write/latest

Test location	/workspace/coverage/default/19.kmac_edn_timeout_error.3101113513
Short name	T999
Test name
Test status
Simulation time	40650456 ps
CPU time	1.21 seconds
Started	Jun 04 02:27:09 PM PDT 24
Finished	Jun 04 02:27:11 PM PDT 24
Peak memory	223608 kb
Host	smart-f40f0182-2484-4e4e-bdb6-bc3afd0330b9
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3101113513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3101113513 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/19.kmac_entropy_mode_error.4133265121
Short name	T1006
Test name
Test status
Simulation time	19550069 ps
CPU time	1.01 seconds
Started	Jun 04 02:27:08 PM PDT 24
Finished	Jun 04 02:27:09 PM PDT 24
Peak memory	218848 kb
Host	smart-76ec6a1a-0f14-4ece-b443-d8f9fdcc651c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4133265121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.4133265121 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/19.kmac_entropy_refresh.3274984366
Short name	T432
Test name
Test status
Simulation time	26279392675 ps
CPU time	320.7 seconds
Started	Jun 04 02:27:07 PM PDT 24
Finished	Jun 04 02:32:28 PM PDT 24
Peak memory	248856 kb
Host	smart-5a33d90c-151f-4f3a-a946-9eb553e9586d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3274984366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.3274984366 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/19.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/19.kmac_error.1089317154
Short name	T269
Test name
Test status
Simulation time	2758523767 ps
CPU time	69.97 seconds
Started	Jun 04 02:27:08 PM PDT 24
Finished	Jun 04 02:28:18 PM PDT 24
Peak memory	239368 kb
Host	smart-d15e34bf-7b82-4980-b8f0-65ddb4b3e334
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1089317154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.1089317154 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_error/latest

Test location	/workspace/coverage/default/19.kmac_key_error.3259930302
Short name	T587
Test name
Test status
Simulation time	747140676 ps
CPU time	6.05 seconds
Started	Jun 04 02:27:09 PM PDT 24
Finished	Jun 04 02:27:15 PM PDT 24
Peak memory	223608 kb
Host	smart-5099aacd-f2e9-4b85-bfa1-96919c3374d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3259930302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.3259930302 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_key_error/latest

Test location	/workspace/coverage/default/19.kmac_lc_escalation.2619053256
Short name	T712
Test name
Test status
Simulation time	51988038 ps
CPU time	1.53 seconds
Started	Jun 04 02:27:17 PM PDT 24
Finished	Jun 04 02:27:19 PM PDT 24
Peak memory	227320 kb
Host	smart-5619b0b8-aeb1-49a1-8db5-75b43abd5be3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2619053256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.2619053256 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/19.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/19.kmac_long_msg_and_output.2296811527
Short name	T611
Test name
Test status
Simulation time	36331613114 ps
CPU time	1815.76 seconds
Started	Jun 04 02:26:55 PM PDT 24
Finished	Jun 04 02:57:12 PM PDT 24
Peak memory	393972 kb
Host	smart-c97ec49c-cd33-438d-9172-b4a9dbe8c1fb
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296811527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a nd_output.2296811527 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/19.kmac_sideload.2179449465
Short name	T615
Test name
Test status
Simulation time	3230096262 ps
CPU time	75.47 seconds
Started	Jun 04 02:26:56 PM PDT 24
Finished	Jun 04 02:28:12 PM PDT 24
Peak memory	230040 kb
Host	smart-a7352194-5434-45d6-84ac-fb0f03e37d9a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179449465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2179449465 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_sideload/latest

Test location	/workspace/coverage/default/19.kmac_smoke.2183413695
Short name	T655
Test name
Test status
Simulation time	503428871 ps
CPU time	11.27 seconds
Started	Jun 04 02:26:55 PM PDT 24
Finished	Jun 04 02:27:07 PM PDT 24
Peak memory	226724 kb
Host	smart-8170f2ce-aa48-48f7-90f7-b21b667f8a2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2183413695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.2183413695 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_smoke/latest

Test location	/workspace/coverage/default/19.kmac_stress_all.1140846655
Short name	T590
Test name
Test status
Simulation time	1199056054 ps
CPU time	84.69 seconds
Started	Jun 04 02:27:16 PM PDT 24
Finished	Jun 04 02:28:41 PM PDT 24
Peak memory	242032 kb
Host	smart-ac515275-6b36-460f-88e7-08dc8a911f21
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1140846655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.1140846655 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_stress_all/latest

Test location	/workspace/coverage/default/19.kmac_stress_all_with_rand_reset.3687775101
Short name	T854
Test name
Test status
Simulation time	406170620539 ps
CPU time	1828.68 seconds
Started	Jun 04 02:27:20 PM PDT 24
Finished	Jun 04 02:57:50 PM PDT 24
Peak memory	322092 kb
Host	smart-c4d0e87e-560d-4c9c-9e04-f8425c7dc0c1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3687775101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all_with_rand_reset.3687775101 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_kmac.2872289306
Short name	T629
Test name
Test status
Simulation time	514130515 ps
CPU time	6.23 seconds
Started	Jun 04 02:27:10 PM PDT 24
Finished	Jun 04 02:27:16 PM PDT 24
Peak memory	219264 kb
Host	smart-b91db7bf-135a-4935-818c-000aab3f1e44
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872289306 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.kmac_test_vectors_kmac.2872289306 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_kmac_xof.2584150778
Short name	T931
Test name
Test status
Simulation time	1050623408 ps
CPU time	6.8 seconds
Started	Jun 04 02:27:09 PM PDT 24
Finished	Jun 04 02:27:16 PM PDT 24
Peak memory	219292 kb
Host	smart-d3555d0e-5615-4335-8e4c-29b545a315cf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584150778 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_kmac_xof.2584150778 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_224.3068993330
Short name	T265
Test name
Test status
Simulation time	226314552354 ps
CPU time	2424 seconds
Started	Jun 04 02:27:03 PM PDT 24
Finished	Jun 04 03:07:28 PM PDT 24
Peak memory	399496 kb
Host	smart-cac1e35c-fa9c-4551-8ccc-7d81473be8d3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3068993330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.3068993330 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_256.947752320
Short name	T219
Test name
Test status
Simulation time	62666809229 ps
CPU time	2007.53 seconds
Started	Jun 04 02:27:01 PM PDT 24
Finished	Jun 04 03:00:30 PM PDT 24
Peak memory	385672 kb
Host	smart-73898e21-04c2-40fa-8db6-6f2b518c35a2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=947752320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.947752320 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_384.1576920275
Short name	T796
Test name
Test status
Simulation time	94045316262 ps
CPU time	1755.86 seconds
Started	Jun 04 02:27:00 PM PDT 24
Finished	Jun 04 02:56:17 PM PDT 24
Peak memory	333188 kb
Host	smart-6bf1a9e0-6042-4ae7-b570-8dd20996480a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1576920275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.1576920275 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_512.3073220300
Short name	T215
Test name
Test status
Simulation time	11124175893 ps
CPU time	1207.41 seconds
Started	Jun 04 02:27:03 PM PDT 24
Finished	Jun 04 02:47:11 PM PDT 24
Peak memory	303376 kb
Host	smart-fbfc1636-e3d1-41cb-a323-9d7a811c95c3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3073220300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.3073220300 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_shake_128.615391215
Short name	T987
Test name
Test status
Simulation time	1253624509799 ps
CPU time	6362.99 seconds
Started	Jun 04 02:27:00 PM PDT 24
Finished	Jun 04 04:13:05 PM PDT 24
Peak memory	653092 kb
Host	smart-d445750f-3e7d-4fe8-a54b-7eacf11aa718
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=615391215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.615391215 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_shake_256.82826709
Short name	T783
Test name
Test status
Simulation time	567776553487 ps
CPU time	4570.52 seconds
Started	Jun 04 02:27:01 PM PDT 24
Finished	Jun 04 03:43:13 PM PDT 24
Peak memory	568316 kb
Host	smart-90da36c6-8e37-4b1c-a1e7-df59b18afc39
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=82826709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.82826709 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/2.kmac_alert_test.2218040673
Short name	T181
Test name
Test status
Simulation time	26024122 ps
CPU time	0.84 seconds
Started	Jun 04 02:23:38 PM PDT 24
Finished	Jun 04 02:23:40 PM PDT 24
Peak memory	218952 kb
Host	smart-da96ba6a-6d39-4be1-a155-a20fd9c6ffc3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218040673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.2218040673 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_alert_test/latest

Test location	/workspace/coverage/default/2.kmac_app.1740636006
Short name	T850
Test name
Test status
Simulation time	2366386391 ps
CPU time	64.06 seconds
Started	Jun 04 02:23:32 PM PDT 24
Finished	Jun 04 02:24:37 PM PDT 24
Peak memory	229680 kb
Host	smart-dbc93c68-a0c8-4002-9974-85ffb05ed4d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740636006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1740636006 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_app/latest

Test location	/workspace/coverage/default/2.kmac_app_with_partial_data.3972465613
Short name	T218
Test name
Test status
Simulation time	62764279633 ps
CPU time	409.03 seconds
Started	Jun 04 02:23:33 PM PDT 24
Finished	Jun 04 02:30:22 PM PDT 24
Peak memory	253604 kb
Host	smart-45b59971-fd55-4eec-b244-31834d3efa37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3972465613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.3972465613 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/2.kmac_burst_write.3271084030
Short name	T278
Test name
Test status
Simulation time	8064994759 ps
CPU time	946.27 seconds
Started	Jun 04 02:23:32 PM PDT 24
Finished	Jun 04 02:39:19 PM PDT 24
Peak memory	235128 kb
Host	smart-f0f020c2-d9b7-4a8d-811a-55efc662a393
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3271084030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3271084030 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_burst_write/latest

Test location	/workspace/coverage/default/2.kmac_edn_timeout_error.615006596
Short name	T910
Test name
Test status
Simulation time	374629460 ps
CPU time	6.24 seconds
Started	Jun 04 02:23:34 PM PDT 24
Finished	Jun 04 02:23:40 PM PDT 24
Peak memory	222896 kb
Host	smart-ab1e81ad-037e-44da-b551-909b4b932b73
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=615006596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.615006596 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_mode_error.1454764537
Short name	T392
Test name
Test status
Simulation time	66569693 ps
CPU time	0.92 seconds
Started	Jun 04 02:23:30 PM PDT 24
Finished	Jun 04 02:23:32 PM PDT 24
Peak memory	218844 kb
Host	smart-576f6c30-6aca-4629-8bc7-343f775d9f9a
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1454764537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.1454764537 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_ready_error.3200288564
Short name	T10
Test name
Test status
Simulation time	3788143246 ps
CPU time	4.79 seconds
Started	Jun 04 02:23:34 PM PDT 24
Finished	Jun 04 02:23:39 PM PDT 24
Peak memory	227476 kb
Host	smart-9b49a142-9aab-4547-9aea-2ce7602468a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3200288564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3200288564 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/2.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_refresh.339843492
Short name	T68
Test name
Test status
Simulation time	10456647409 ps
CPU time	187.24 seconds
Started	Jun 04 02:23:35 PM PDT 24
Finished	Jun 04 02:26:43 PM PDT 24
Peak memory	240392 kb
Host	smart-8819a3ae-89d6-4532-86db-004e1bac9539
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=339843492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.339843492 +enable_masking=1 +sw_ key_masked=0
Directory	/workspace/2.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/2.kmac_error.3539891798
Short name	T935
Test name
Test status
Simulation time	93097919635 ps
CPU time	474.99 seconds
Started	Jun 04 02:23:33 PM PDT 24
Finished	Jun 04 02:31:28 PM PDT 24
Peak memory	260424 kb
Host	smart-00f83c04-923d-4a56-a9e8-292fd11397c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3539891798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.3539891798 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_error/latest

Test location	/workspace/coverage/default/2.kmac_key_error.3863880156
Short name	T382
Test name
Test status
Simulation time	644874059 ps
CPU time	6.64 seconds
Started	Jun 04 02:23:29 PM PDT 24
Finished	Jun 04 02:23:37 PM PDT 24
Peak memory	225308 kb
Host	smart-8715a343-eec1-441f-9e22-30e7b470ad5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3863880156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.3863880156 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_key_error/latest

Test location	/workspace/coverage/default/2.kmac_lc_escalation.3055095338
Short name	T786
Test name
Test status
Simulation time	90232161 ps
CPU time	1.42 seconds
Started	Jun 04 02:23:30 PM PDT 24
Finished	Jun 04 02:23:32 PM PDT 24
Peak memory	227320 kb
Host	smart-3cc9316e-d374-4c26-80ec-92789a503a74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3055095338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.3055095338 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/2.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/2.kmac_long_msg_and_output.2890727564
Short name	T948
Test name
Test status
Simulation time	282514762222 ps
CPU time	1736.52 seconds
Started	Jun 04 02:23:30 PM PDT 24
Finished	Jun 04 02:52:27 PM PDT 24
Peak memory	381164 kb
Host	smart-bd15ab82-f99c-4533-8a88-5634c7347cdf
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890727564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an d_output.2890727564 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/2.kmac_mubi.238479974
Short name	T54
Test name
Test status
Simulation time	16300139527 ps
CPU time	122.83 seconds
Started	Jun 04 02:23:34 PM PDT 24
Finished	Jun 04 02:25:37 PM PDT 24
Peak memory	236384 kb
Host	smart-00cd0299-7964-422f-9fd8-22ab6666a2c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=238479974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.238479974 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_mubi/latest

Test location	/workspace/coverage/default/2.kmac_sec_cm.725851430
Short name	T84
Test name
Test status
Simulation time	7566426055 ps
CPU time	52.55 seconds
Started	Jun 04 02:23:38 PM PDT 24
Finished	Jun 04 02:24:31 PM PDT 24
Peak memory	266748 kb
Host	smart-d5e622d3-0ff1-4dac-8cec-011abd94520d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725851430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.725851430 +enable_masking =1 +sw_key_masked=0
Directory	/workspace/2.kmac_sec_cm/latest

Test location	/workspace/coverage/default/2.kmac_sideload.2399635089
Short name	T354
Test name
Test status
Simulation time	19153549587 ps
CPU time	317.83 seconds
Started	Jun 04 02:23:31 PM PDT 24
Finished	Jun 04 02:28:50 PM PDT 24
Peak memory	249240 kb
Host	smart-4cce8b08-a4f8-4460-8ec1-63e879a86352
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399635089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.2399635089 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_sideload/latest

Test location	/workspace/coverage/default/2.kmac_smoke.3581822631
Short name	T994
Test name
Test status
Simulation time	1520559203 ps
CPU time	47.1 seconds
Started	Jun 04 02:23:30 PM PDT 24
Finished	Jun 04 02:24:18 PM PDT 24
Peak memory	223488 kb
Host	smart-aecd17e4-e215-4bea-8bdf-9b63a49ed8ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3581822631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3581822631 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_smoke/latest

Test location	/workspace/coverage/default/2.kmac_stress_all.672051816
Short name	T555
Test name
Test status
Simulation time	17582866345 ps
CPU time	1623.28 seconds
Started	Jun 04 02:23:37 PM PDT 24
Finished	Jun 04 02:50:42 PM PDT 24
Peak memory	377756 kb
Host	smart-81cac03d-f68c-4825-a878-607c8b4b66d7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=672051816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.672051816 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_stress_all/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_kmac.3913595143
Short name	T738
Test name
Test status
Simulation time	790496239 ps
CPU time	6.32 seconds
Started	Jun 04 02:23:36 PM PDT 24
Finished	Jun 04 02:23:43 PM PDT 24
Peak memory	219384 kb
Host	smart-c67067b1-9b43-4152-ab67-6087e01ff4d8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913595143 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.kmac_test_vectors_kmac.3913595143 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_kmac_xof.4110420915
Short name	T207
Test name
Test status
Simulation time	420940081 ps
CPU time	5.56 seconds
Started	Jun 04 02:23:30 PM PDT 24
Finished	Jun 04 02:23:36 PM PDT 24
Peak memory	220228 kb
Host	smart-a9d6fb73-ccac-4095-ae8a-78e7178006aa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110420915 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.4110420915 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_224.320615633
Short name	T245
Test name
Test status
Simulation time	102506303172 ps
CPU time	2231.16 seconds
Started	Jun 04 02:23:37 PM PDT 24
Finished	Jun 04 03:00:50 PM PDT 24
Peak memory	391500 kb
Host	smart-e8d0dd1d-3316-4654-bf34-3218a7faff84
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=320615633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.320615633 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_256.589874926
Short name	T183
Test name
Test status
Simulation time	381467737625 ps
CPU time	2341.22 seconds
Started	Jun 04 02:23:31 PM PDT 24
Finished	Jun 04 03:02:33 PM PDT 24
Peak memory	387540 kb
Host	smart-7a209b0a-6e28-43f6-97a1-b618fb6d9a42
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=589874926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.589874926 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_384.5077129
Short name	T352
Test name
Test status
Simulation time	54224542307 ps
CPU time	1509.64 seconds
Started	Jun 04 02:23:36 PM PDT 24
Finished	Jun 04 02:48:46 PM PDT 24
Peak memory	348028 kb
Host	smart-4d2a35f1-ab6b-4462-8c93-55cfd70f5304
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=5077129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.5077129 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_512.1355195461
Short name	T184
Test name
Test status
Simulation time	90190785637 ps
CPU time	1271.53 seconds
Started	Jun 04 02:23:29 PM PDT 24
Finished	Jun 04 02:44:41 PM PDT 24
Peak memory	303616 kb
Host	smart-abec6036-04ae-4d9a-b2eb-88d8ed05b41e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1355195461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1355195461 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_shake_128.4021021384
Short name	T1011
Test name
Test status
Simulation time	122028778355 ps
CPU time	5331.26 seconds
Started	Jun 04 02:23:32 PM PDT 24
Finished	Jun 04 03:52:25 PM PDT 24
Peak memory	652220 kb
Host	smart-fc9db4e0-fa8f-424c-84ef-7293f77b3dba
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4021021384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.4021021384 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_shake_256.1378655383
Short name	T281
Test name
Test status
Simulation time	153881179124 ps
CPU time	5027.59 seconds
Started	Jun 04 02:23:30 PM PDT 24
Finished	Jun 04 03:47:19 PM PDT 24
Peak memory	581612 kb
Host	smart-834070a5-73a8-4f01-88e1-0e97de711071
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1378655383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.1378655383 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/20.kmac_alert_test.2979938665
Short name	T742
Test name
Test status
Simulation time	47014563 ps
CPU time	0.84 seconds
Started	Jun 04 02:27:27 PM PDT 24
Finished	Jun 04 02:27:29 PM PDT 24
Peak memory	218952 kb
Host	smart-8d38c5e1-f699-4eb6-ab19-b96f687d29a5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979938665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.2979938665 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_alert_test/latest

Test location	/workspace/coverage/default/20.kmac_app.4259098036
Short name	T300
Test name
Test status
Simulation time	18200743987 ps
CPU time	213 seconds
Started	Jun 04 02:27:24 PM PDT 24
Finished	Jun 04 02:30:58 PM PDT 24
Peak memory	241056 kb
Host	smart-af9804b1-b700-40e5-9d06-03cfb84768a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4259098036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.4259098036 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_app/latest

Test location	/workspace/coverage/default/20.kmac_burst_write.2821122653
Short name	T144
Test name
Test status
Simulation time	15968279835 ps
CPU time	645.92 seconds
Started	Jun 04 02:27:14 PM PDT 24
Finished	Jun 04 02:38:01 PM PDT 24
Peak memory	242280 kb
Host	smart-7fd0e0dc-d3b6-4af1-8fde-1657edd0d4aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2821122653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.2821122653 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_burst_write/latest

Test location	/workspace/coverage/default/20.kmac_entropy_refresh.45817771
Short name	T268
Test name
Test status
Simulation time	31977960021 ps
CPU time	113.35 seconds
Started	Jun 04 02:27:34 PM PDT 24
Finished	Jun 04 02:29:28 PM PDT 24
Peak memory	234032 kb
Host	smart-07966cbe-52d1-4b76-a666-9dd5451c0da6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=45817771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.45817771 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/20.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/20.kmac_key_error.100896989
Short name	T389
Test name
Test status
Simulation time	5922526041 ps
CPU time	13.57 seconds
Started	Jun 04 02:27:21 PM PDT 24
Finished	Jun 04 02:27:35 PM PDT 24
Peak memory	225580 kb
Host	smart-058b8d00-ccd0-4a9c-adb4-ed30436e9ebe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=100896989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.100896989 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_key_error/latest

Test location	/workspace/coverage/default/20.kmac_long_msg_and_output.862747770
Short name	T1030
Test name
Test status
Simulation time	3669038690 ps
CPU time	365.98 seconds
Started	Jun 04 02:27:14 PM PDT 24
Finished	Jun 04 02:33:21 PM PDT 24
Peak memory	256836 kb
Host	smart-0ac13d1e-4b89-4fed-a070-8c029d34c5e2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862747770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_an d_output.862747770 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/20.kmac_sideload.2183774668
Short name	T498
Test name
Test status
Simulation time	1722414886 ps
CPU time	26.67 seconds
Started	Jun 04 02:27:16 PM PDT 24
Finished	Jun 04 02:27:43 PM PDT 24
Peak memory	227304 kb
Host	smart-146842b0-a2e8-42e4-afa6-9d7450b51fe8
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183774668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.2183774668 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_sideload/latest

Test location	/workspace/coverage/default/20.kmac_smoke.1489054133
Short name	T214
Test name
Test status
Simulation time	9872070669 ps
CPU time	84.77 seconds
Started	Jun 04 02:27:14 PM PDT 24
Finished	Jun 04 02:28:39 PM PDT 24
Peak memory	227424 kb
Host	smart-307036c1-b1a7-4ffd-8cfc-9e15360a4f1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489054133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.1489054133 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_smoke/latest

Test location	/workspace/coverage/default/20.kmac_stress_all.1609368500
Short name	T597
Test name
Test status
Simulation time	302483711421 ps
CPU time	2054.15 seconds
Started	Jun 04 02:27:24 PM PDT 24
Finished	Jun 04 03:01:39 PM PDT 24
Peak memory	395828 kb
Host	smart-e9e6bf19-ef83-4335-b0c1-b9bc87ab4044
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1609368500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.1609368500 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_stress_all/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_kmac.3978997554
Short name	T614
Test name
Test status
Simulation time	273852761 ps
CPU time	6.1 seconds
Started	Jun 04 02:27:23 PM PDT 24
Finished	Jun 04 02:27:30 PM PDT 24
Peak memory	220232 kb
Host	smart-dcc56dc1-bea2-47b7-a154-d0039b33b2a7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978997554 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 20.kmac_test_vectors_kmac.3978997554 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_kmac_xof.2013068284
Short name	T364
Test name
Test status
Simulation time	476567893 ps
CPU time	5.37 seconds
Started	Jun 04 02:27:23 PM PDT 24
Finished	Jun 04 02:27:28 PM PDT 24
Peak memory	219344 kb
Host	smart-fbc85c67-1097-46b3-a546-03585ce2160e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013068284 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_kmac_xof.2013068284 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_224.3165982183
Short name	T113
Test name
Test status
Simulation time	134166704365 ps
CPU time	2185.45 seconds
Started	Jun 04 02:27:15 PM PDT 24
Finished	Jun 04 03:03:41 PM PDT 24
Peak memory	394036 kb
Host	smart-5655bb0d-c1c4-4ef1-a4ea-50adf4da399c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3165982183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.3165982183 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_256.3285537359
Short name	T196
Test name
Test status
Simulation time	95544991284 ps
CPU time	2367.87 seconds
Started	Jun 04 02:27:18 PM PDT 24
Finished	Jun 04 03:06:47 PM PDT 24
Peak memory	386868 kb
Host	smart-754fd754-5e1c-4679-8aa1-8cb88899f86d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3285537359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.3285537359 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_384.98940661
Short name	T255
Test name
Test status
Simulation time	76187805223 ps
CPU time	1626.5 seconds
Started	Jun 04 02:27:15 PM PDT 24
Finished	Jun 04 02:54:22 PM PDT 24
Peak memory	334328 kb
Host	smart-7123f69c-a5b3-4928-8d13-a59780732792
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=98940661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.98940661 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_512.1217682115
Short name	T453
Test name
Test status
Simulation time	197347767407 ps
CPU time	1284.96 seconds
Started	Jun 04 02:27:21 PM PDT 24
Finished	Jun 04 02:48:47 PM PDT 24
Peak memory	302036 kb
Host	smart-fb467176-f1ff-4ff5-aa66-69a26a79a97c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1217682115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.1217682115 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_shake_128.3495702258
Short name	T395
Test name
Test status
Simulation time	185568118524 ps
CPU time	5837.66 seconds
Started	Jun 04 02:27:23 PM PDT 24
Finished	Jun 04 04:04:41 PM PDT 24
Peak memory	666816 kb
Host	smart-15a9fe24-1d87-4c2d-b35d-0323fb53d92d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3495702258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.3495702258 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_shake_256.3490071338
Short name	T671
Test name
Test status
Simulation time	803351459660 ps
CPU time	5318.17 seconds
Started	Jun 04 02:27:23 PM PDT 24
Finished	Jun 04 03:56:02 PM PDT 24
Peak memory	582712 kb
Host	smart-03d4ad51-6ecd-4472-b8a7-ef07d4b6164d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3490071338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.3490071338 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/21.kmac_alert_test.3206772565
Short name	T674
Test name
Test status
Simulation time	42669296 ps
CPU time	0.84 seconds
Started	Jun 04 02:27:44 PM PDT 24
Finished	Jun 04 02:27:46 PM PDT 24
Peak memory	218908 kb
Host	smart-d3a64934-2a08-4688-9077-e4a40f5834c1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206772565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.3206772565 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_alert_test/latest

Test location	/workspace/coverage/default/21.kmac_app.3331521936
Short name	T285
Test name
Test status
Simulation time	18629724122 ps
CPU time	288.08 seconds
Started	Jun 04 02:27:35 PM PDT 24
Finished	Jun 04 02:32:24 PM PDT 24
Peak memory	250596 kb
Host	smart-5139e261-91dd-4fef-95de-4a468b0e9ab6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3331521936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3331521936 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_app/latest

Test location	/workspace/coverage/default/21.kmac_burst_write.2423581400
Short name	T38
Test name
Test status
Simulation time	20505079702 ps
CPU time	1099.38 seconds
Started	Jun 04 02:27:28 PM PDT 24
Finished	Jun 04 02:45:48 PM PDT 24
Peak memory	243884 kb
Host	smart-df707a7d-251d-4c57-8c8f-a295cb81da66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423581400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.2423581400 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_burst_write/latest

Test location	/workspace/coverage/default/21.kmac_entropy_refresh.3986043202
Short name	T1020
Test name
Test status
Simulation time	49360416241 ps
CPU time	307.17 seconds
Started	Jun 04 02:27:36 PM PDT 24
Finished	Jun 04 02:32:43 PM PDT 24
Peak memory	245492 kb
Host	smart-a8eebf99-273a-4dff-9963-4a2afd75e365
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986043202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.3986043202 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/21.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/21.kmac_error.2572945533
Short name	T420
Test name
Test status
Simulation time	8384738464 ps
CPU time	191 seconds
Started	Jun 04 02:27:35 PM PDT 24
Finished	Jun 04 02:30:47 PM PDT 24
Peak memory	259832 kb
Host	smart-d3cc5dad-6f90-4e4d-b3b4-718baa122f87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2572945533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.2572945533 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_error/latest

Test location	/workspace/coverage/default/21.kmac_key_error.917366056
Short name	T811
Test name
Test status
Simulation time	1739288784 ps
CPU time	13.54 seconds
Started	Jun 04 02:27:34 PM PDT 24
Finished	Jun 04 02:27:48 PM PDT 24
Peak memory	219012 kb
Host	smart-bc09f158-b4ec-4eb4-83bf-d5cfa09caa89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=917366056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.917366056 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_key_error/latest

Test location	/workspace/coverage/default/21.kmac_lc_escalation.1848870719
Short name	T909
Test name
Test status
Simulation time	42516535 ps
CPU time	1.44 seconds
Started	Jun 04 02:27:35 PM PDT 24
Finished	Jun 04 02:27:37 PM PDT 24
Peak memory	227244 kb
Host	smart-d616a8b9-dec0-49e6-88d5-8a238863a794
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1848870719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.1848870719 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/21.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/21.kmac_long_msg_and_output.1240528729
Short name	T656
Test name
Test status
Simulation time	72341132676 ps
CPU time	1212.45 seconds
Started	Jun 04 02:27:29 PM PDT 24
Finished	Jun 04 02:47:42 PM PDT 24
Peak memory	329112 kb
Host	smart-b01722bd-4e22-4831-99b4-15d91574c658
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240528729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a nd_output.1240528729 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/21.kmac_sideload.3553045593
Short name	T1015
Test name
Test status
Simulation time	16248009896 ps
CPU time	87.74 seconds
Started	Jun 04 02:27:27 PM PDT 24
Finished	Jun 04 02:28:56 PM PDT 24
Peak memory	230388 kb
Host	smart-3176d142-2ccd-4039-8f9f-18eb1a599a51
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553045593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.3553045593 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_sideload/latest

Test location	/workspace/coverage/default/21.kmac_smoke.3498279390
Short name	T855
Test name
Test status
Simulation time	5770699892 ps
CPU time	53.72 seconds
Started	Jun 04 02:27:33 PM PDT 24
Finished	Jun 04 02:28:27 PM PDT 24
Peak memory	227472 kb
Host	smart-91804179-dc66-4661-b55a-f3715c28254d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3498279390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.3498279390 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_smoke/latest

Test location	/workspace/coverage/default/21.kmac_stress_all.3031519089
Short name	T761
Test name
Test status
Simulation time	24480651175 ps
CPU time	340.42 seconds
Started	Jun 04 02:27:36 PM PDT 24
Finished	Jun 04 02:33:17 PM PDT 24
Peak memory	285044 kb
Host	smart-ebf1c280-38a8-4046-8704-0bf40643c571
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3031519089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.3031519089 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_stress_all/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_kmac.3100111340
Short name	T779
Test name
Test status
Simulation time	191612862 ps
CPU time	6.07 seconds
Started	Jun 04 02:27:34 PM PDT 24
Finished	Jun 04 02:27:41 PM PDT 24
Peak memory	220244 kb
Host	smart-2aeda5c5-bf91-4071-8a84-081739ce2372
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100111340 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 21.kmac_test_vectors_kmac.3100111340 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_kmac_xof.2779266964
Short name	T596
Test name
Test status
Simulation time	345638765 ps
CPU time	6.2 seconds
Started	Jun 04 02:27:34 PM PDT 24
Finished	Jun 04 02:27:41 PM PDT 24
Peak memory	219224 kb
Host	smart-f5802245-9a4f-4e36-b9c6-e7f6742ae339
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779266964 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_kmac_xof.2779266964 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_224.2321425196
Short name	T788
Test name
Test status
Simulation time	99833836560 ps
CPU time	2443.78 seconds
Started	Jun 04 02:27:33 PM PDT 24
Finished	Jun 04 03:08:18 PM PDT 24
Peak memory	400508 kb
Host	smart-3eb27c62-6b3b-4d02-af72-dd040bb5c811
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2321425196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.2321425196 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_256.33982304
Short name	T291
Test name
Test status
Simulation time	350887737209 ps
CPU time	2088.52 seconds
Started	Jun 04 02:27:33 PM PDT 24
Finished	Jun 04 03:02:22 PM PDT 24
Peak memory	391852 kb
Host	smart-95774545-dc91-4b08-8e4a-5d694a55cb46
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=33982304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.33982304 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_384.3172942723
Short name	T358
Test name
Test status
Simulation time	95309861083 ps
CPU time	1745.51 seconds
Started	Jun 04 02:27:27 PM PDT 24
Finished	Jun 04 02:56:34 PM PDT 24
Peak memory	345516 kb
Host	smart-61d8348b-375e-4241-a07c-d183ab658185
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3172942723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.3172942723 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_512.2935989258
Short name	T445
Test name
Test status
Simulation time	139287825822 ps
CPU time	1235.6 seconds
Started	Jun 04 02:27:36 PM PDT 24
Finished	Jun 04 02:48:12 PM PDT 24
Peak memory	303636 kb
Host	smart-0885c009-9a03-4153-bae6-b13541f31804
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2935989258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.2935989258 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_shake_128.3100236389
Short name	T1064
Test name
Test status
Simulation time	1727237193450 ps
CPU time	6472.12 seconds
Started	Jun 04 02:27:37 PM PDT 24
Finished	Jun 04 04:15:30 PM PDT 24
Peak memory	654196 kb
Host	smart-3a3da2ad-390b-45c4-a3e0-d8baf9a5d30e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3100236389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.3100236389 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_shake_256.802491290
Short name	T398
Test name
Test status
Simulation time	157093111935 ps
CPU time	4704.98 seconds
Started	Jun 04 02:27:35 PM PDT 24
Finished	Jun 04 03:46:01 PM PDT 24
Peak memory	565296 kb
Host	smart-776e9f5a-3b32-41f2-834c-78707918d4e9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=802491290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.802491290 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/22.kmac_alert_test.3777467741
Short name	T1016
Test name
Test status
Simulation time	21977067 ps
CPU time	0.83 seconds
Started	Jun 04 02:27:59 PM PDT 24
Finished	Jun 04 02:28:00 PM PDT 24
Peak memory	218924 kb
Host	smart-4060c8d0-455e-42bf-b08c-4df29b923f4e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777467741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.3777467741 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_alert_test/latest

Test location	/workspace/coverage/default/22.kmac_app.742345676
Short name	T993
Test name
Test status
Simulation time	7177045644 ps
CPU time	378.22 seconds
Started	Jun 04 02:27:51 PM PDT 24
Finished	Jun 04 02:34:10 PM PDT 24
Peak memory	252992 kb
Host	smart-ac82fa4e-b048-434b-a813-287996e145da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=742345676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.742345676 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_app/latest

Test location	/workspace/coverage/default/22.kmac_burst_write.1820684630
Short name	T496
Test name
Test status
Simulation time	54467449346 ps
CPU time	1477.79 seconds
Started	Jun 04 02:27:44 PM PDT 24
Finished	Jun 04 02:52:23 PM PDT 24
Peak memory	238872 kb
Host	smart-4f0d7118-b3fb-422a-a291-8edb943ca935
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1820684630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.1820684630 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_burst_write/latest

Test location	/workspace/coverage/default/22.kmac_entropy_refresh.2353053068
Short name	T982
Test name
Test status
Simulation time	53249901629 ps
CPU time	283.62 seconds
Started	Jun 04 02:27:51 PM PDT 24
Finished	Jun 04 02:32:35 PM PDT 24
Peak memory	247628 kb
Host	smart-d2f597b5-2b28-4192-83be-ae616870ce9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2353053068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.2353053068 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/22.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/22.kmac_error.1042784731
Short name	T108
Test name
Test status
Simulation time	15990692706 ps
CPU time	39.67 seconds
Started	Jun 04 02:27:51 PM PDT 24
Finished	Jun 04 02:28:31 PM PDT 24
Peak memory	240920 kb
Host	smart-afa78098-9c3a-4fe7-9f3b-329a9c37685e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1042784731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.1042784731 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_error/latest

Test location	/workspace/coverage/default/22.kmac_key_error.1770018317
Short name	T347
Test name
Test status
Simulation time	3087668646 ps
CPU time	12.65 seconds
Started	Jun 04 02:27:57 PM PDT 24
Finished	Jun 04 02:28:10 PM PDT 24
Peak memory	226024 kb
Host	smart-c1cbd8e6-f796-49b4-8d2c-a8c3d61f7e00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770018317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1770018317 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_key_error/latest

Test location	/workspace/coverage/default/22.kmac_lc_escalation.3732771809
Short name	T31
Test name
Test status
Simulation time	630706497 ps
CPU time	16.23 seconds
Started	Jun 04 02:27:56 PM PDT 24
Finished	Jun 04 02:28:13 PM PDT 24
Peak memory	235676 kb
Host	smart-e68f289c-6b30-4d34-858e-b34a9422445d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3732771809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.3732771809 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/22.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/22.kmac_long_msg_and_output.3210937641
Short name	T384
Test name
Test status
Simulation time	123166070980 ps
CPU time	1010.11 seconds
Started	Jun 04 02:27:45 PM PDT 24
Finished	Jun 04 02:44:36 PM PDT 24
Peak memory	305868 kb
Host	smart-26956eea-867a-4d13-be29-16f209b1e34b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210937641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a nd_output.3210937641 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/22.kmac_sideload.2898925244
Short name	T640
Test name
Test status
Simulation time	50829567392 ps
CPU time	534.01 seconds
Started	Jun 04 02:27:45 PM PDT 24
Finished	Jun 04 02:36:40 PM PDT 24
Peak memory	256828 kb
Host	smart-00ea39a0-e8d4-4a64-8abe-93ad822051d7
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898925244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2898925244 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_sideload/latest

Test location	/workspace/coverage/default/22.kmac_smoke.3218077014
Short name	T1018
Test name
Test status
Simulation time	3056504665 ps
CPU time	30.04 seconds
Started	Jun 04 02:27:44 PM PDT 24
Finished	Jun 04 02:28:15 PM PDT 24
Peak memory	226876 kb
Host	smart-9b1fc013-e160-4084-b14a-3d00e78059c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3218077014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.3218077014 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_smoke/latest

Test location	/workspace/coverage/default/22.kmac_stress_all.3916161943
Short name	T631
Test name
Test status
Simulation time	636799179 ps
CPU time	14.94 seconds
Started	Jun 04 02:27:56 PM PDT 24
Finished	Jun 04 02:28:12 PM PDT 24
Peak memory	236364 kb
Host	smart-e50521df-590a-4e3b-900c-8d13d3ea12e5
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3916161943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.3916161943 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_stress_all/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_kmac.1061993511
Short name	T669
Test name
Test status
Simulation time	1395207027 ps
CPU time	6.8 seconds
Started	Jun 04 02:27:53 PM PDT 24
Finished	Jun 04 02:28:00 PM PDT 24
Peak memory	220216 kb
Host	smart-0adbc252-61ab-47d3-a67c-a4df6c3f20ce
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061993511 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.kmac_test_vectors_kmac.1061993511 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_kmac_xof.2786749302
Short name	T1004
Test name
Test status
Simulation time	1061751856 ps
CPU time	7.01 seconds
Started	Jun 04 02:27:51 PM PDT 24
Finished	Jun 04 02:27:59 PM PDT 24
Peak memory	219292 kb
Host	smart-59353063-8fa1-4cc6-8093-f4b3aa59858b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786749302 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_kmac_xof.2786749302 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_224.642397771
Short name	T201
Test name
Test status
Simulation time	21367223206 ps
CPU time	1977.61 seconds
Started	Jun 04 02:27:44 PM PDT 24
Finished	Jun 04 03:00:43 PM PDT 24
Peak memory	405076 kb
Host	smart-f2be0789-49c7-428e-bbd9-6202cc686297
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=642397771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.642397771 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_256.1226906233
Short name	T814
Test name
Test status
Simulation time	21129283800 ps
CPU time	2032.37 seconds
Started	Jun 04 02:27:44 PM PDT 24
Finished	Jun 04 03:01:38 PM PDT 24
Peak memory	392120 kb
Host	smart-4e174906-8cb5-4979-9332-18c8a93d02ff
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1226906233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.1226906233 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_512.2138237840
Short name	T208
Test name
Test status
Simulation time	13332770070 ps
CPU time	1108.72 seconds
Started	Jun 04 02:27:51 PM PDT 24
Finished	Jun 04 02:46:21 PM PDT 24
Peak memory	295896 kb
Host	smart-1e6a2727-90be-45d1-8b05-c254e53e3a29
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2138237840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.2138237840 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_shake_128.2508924752
Short name	T334
Test name
Test status
Simulation time	381330193288 ps
CPU time	5857.28 seconds
Started	Jun 04 02:27:51 PM PDT 24
Finished	Jun 04 04:05:29 PM PDT 24
Peak memory	651372 kb
Host	smart-4041f001-e890-4b41-96f6-b440eaa66936
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2508924752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.2508924752 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_shake_256.4171794797
Short name	T345
Test name
Test status
Simulation time	118433177634 ps
CPU time	4525.75 seconds
Started	Jun 04 02:27:52 PM PDT 24
Finished	Jun 04 03:43:18 PM PDT 24
Peak memory	567824 kb
Host	smart-b56fcd60-1742-4174-b91b-25b929017251
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4171794797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.4171794797 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/23.kmac_alert_test.2394762408
Short name	T274
Test name
Test status
Simulation time	37306366 ps
CPU time	0.78 seconds
Started	Jun 04 02:28:13 PM PDT 24
Finished	Jun 04 02:28:14 PM PDT 24
Peak memory	218904 kb
Host	smart-7800823f-9329-4484-a410-f8a03a72dafb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394762408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2394762408 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_alert_test/latest

Test location	/workspace/coverage/default/23.kmac_app.2056104890
Short name	T525
Test name
Test status
Simulation time	10516515482 ps
CPU time	144.75 seconds
Started	Jun 04 02:28:13 PM PDT 24
Finished	Jun 04 02:30:39 PM PDT 24
Peak memory	237820 kb
Host	smart-07b535b0-fa5e-40c4-a138-dd74db6ee96d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056104890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.2056104890 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_app/latest

Test location	/workspace/coverage/default/23.kmac_burst_write.4179504437
Short name	T146
Test name
Test status
Simulation time	76771704000 ps
CPU time	487.64 seconds
Started	Jun 04 02:27:56 PM PDT 24
Finished	Jun 04 02:36:05 PM PDT 24
Peak memory	233588 kb
Host	smart-9dadf889-d60e-49e0-8564-495dc3356b3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4179504437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.4179504437 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_burst_write/latest

Test location	/workspace/coverage/default/23.kmac_entropy_refresh.3919579970
Short name	T682
Test name
Test status
Simulation time	1668440380 ps
CPU time	6.38 seconds
Started	Jun 04 02:28:14 PM PDT 24
Finished	Jun 04 02:28:21 PM PDT 24
Peak memory	227348 kb
Host	smart-fe78b6d0-9499-4895-87c0-1ba63369f4b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3919579970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.3919579970 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/23.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/23.kmac_error.1884928730
Short name	T373
Test name
Test status
Simulation time	59837338431 ps
CPU time	384.68 seconds
Started	Jun 04 02:28:13 PM PDT 24
Finished	Jun 04 02:34:39 PM PDT 24
Peak memory	261752 kb
Host	smart-9646ed64-670b-48de-a71e-dc1641e90a19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1884928730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.1884928730 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_error/latest

Test location	/workspace/coverage/default/23.kmac_key_error.1112134955
Short name	T902
Test name
Test status
Simulation time	1344357995 ps
CPU time	9.1 seconds
Started	Jun 04 02:28:12 PM PDT 24
Finished	Jun 04 02:28:22 PM PDT 24
Peak memory	224664 kb
Host	smart-612630dd-53e4-43cd-ab41-be889fc83f8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112134955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.1112134955 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_key_error/latest

Test location	/workspace/coverage/default/23.kmac_long_msg_and_output.2615333662
Short name	T400
Test name
Test status
Simulation time	52810709449 ps
CPU time	478.07 seconds
Started	Jun 04 02:27:58 PM PDT 24
Finished	Jun 04 02:35:57 PM PDT 24
Peak memory	261580 kb
Host	smart-79260378-0041-4c03-a6a1-6646c3c76907
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615333662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a nd_output.2615333662 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/23.kmac_sideload.3610027801
Short name	T734
Test name
Test status
Simulation time	17636103643 ps
CPU time	362.15 seconds
Started	Jun 04 02:27:58 PM PDT 24
Finished	Jun 04 02:34:00 PM PDT 24
Peak memory	250184 kb
Host	smart-a1b96c26-aa65-4ee9-964b-cf20be43d4e1
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610027801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3610027801 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_sideload/latest

Test location	/workspace/coverage/default/23.kmac_smoke.1526146167
Short name	T733
Test name
Test status
Simulation time	4145147603 ps
CPU time	25.48 seconds
Started	Jun 04 02:27:57 PM PDT 24
Finished	Jun 04 02:28:23 PM PDT 24
Peak memory	227456 kb
Host	smart-5b06ec1a-c7e8-42de-abd8-f56fe362eb4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1526146167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1526146167 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_smoke/latest

Test location	/workspace/coverage/default/23.kmac_stress_all.2525055657
Short name	T860
Test name
Test status
Simulation time	10553309787 ps
CPU time	759.58 seconds
Started	Jun 04 02:28:13 PM PDT 24
Finished	Jun 04 02:40:53 PM PDT 24
Peak memory	320024 kb
Host	smart-2c958595-450d-4342-a3a2-9c19a3ab14fd
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2525055657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.2525055657 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_stress_all/latest

Test location	/workspace/coverage/default/23.kmac_stress_all_with_rand_reset.2699092763
Short name	T134
Test name
Test status
Simulation time	29949863854 ps
CPU time	413.36 seconds
Started	Jun 04 02:28:14 PM PDT 24
Finished	Jun 04 02:35:08 PM PDT 24
Peak memory	271164 kb
Host	smart-69c2c3c6-50be-492a-8ce0-83dfa2ce0e1f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2699092763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all_with_rand_reset.2699092763 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_kmac.2915848779
Short name	T436
Test name
Test status
Simulation time	1349745752 ps
CPU time	6.67 seconds
Started	Jun 04 02:28:11 PM PDT 24
Finished	Jun 04 02:28:19 PM PDT 24
Peak memory	220204 kb
Host	smart-2b3a0095-62fb-4703-9eb0-68813087ca91
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915848779 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 23.kmac_test_vectors_kmac.2915848779 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_kmac_xof.4078360790
Short name	T542
Test name
Test status
Simulation time	351710143 ps
CPU time	5.52 seconds
Started	Jun 04 02:28:11 PM PDT 24
Finished	Jun 04 02:28:18 PM PDT 24
Peak memory	220244 kb
Host	smart-d57345a4-7dff-483b-b95f-ee877f55ded1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078360790 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_kmac_xof.4078360790 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_224.1718395876
Short name	T185
Test name
Test status
Simulation time	200813840552 ps
CPU time	2324.26 seconds
Started	Jun 04 02:27:58 PM PDT 24
Finished	Jun 04 03:06:43 PM PDT 24
Peak memory	396632 kb
Host	smart-7eb24a48-1d9f-406b-923e-7f5757b4cb26
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1718395876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.1718395876 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_256.2593299716
Short name	T293
Test name
Test status
Simulation time	20806027771 ps
CPU time	1821.21 seconds
Started	Jun 04 02:28:08 PM PDT 24
Finished	Jun 04 02:58:31 PM PDT 24
Peak memory	385936 kb
Host	smart-56699da9-b63e-4945-a3f3-d74ea2013d20
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2593299716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.2593299716 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_384.3379142331
Short name	T938
Test name
Test status
Simulation time	15031540791 ps
CPU time	1494.99 seconds
Started	Jun 04 02:28:05 PM PDT 24
Finished	Jun 04 02:53:01 PM PDT 24
Peak memory	342896 kb
Host	smart-deabf210-f62b-4bd2-a75a-06e948ea3381
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3379142331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.3379142331 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_512.983236537
Short name	T806
Test name
Test status
Simulation time	75730525988 ps
CPU time	1153.87 seconds
Started	Jun 04 02:28:08 PM PDT 24
Finished	Jun 04 02:47:23 PM PDT 24
Peak memory	300020 kb
Host	smart-72dc5a5f-cb47-45bd-a340-141a5b8fb9ed
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=983236537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.983236537 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_shake_128.1010424609
Short name	T722
Test name
Test status
Simulation time	119838618097 ps
CPU time	5347.81 seconds
Started	Jun 04 02:28:04 PM PDT 24
Finished	Jun 04 03:57:12 PM PDT 24
Peak memory	658216 kb
Host	smart-2830c92c-2970-4a42-bfe8-8722c29011d6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1010424609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.1010424609 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_shake_256.654021690
Short name	T276
Test name
Test status
Simulation time	597947183304 ps
CPU time	5031.17 seconds
Started	Jun 04 02:28:08 PM PDT 24
Finished	Jun 04 03:52:01 PM PDT 24
Peak memory	568552 kb
Host	smart-471a04c9-4d9e-45bc-b805-03586423bedb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=654021690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.654021690 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/24.kmac_alert_test.867597570
Short name	T187
Test name
Test status
Simulation time	30783742 ps
CPU time	0.85 seconds
Started	Jun 04 02:28:31 PM PDT 24
Finished	Jun 04 02:28:32 PM PDT 24
Peak memory	218940 kb
Host	smart-d5f35b50-319f-4f09-8b0d-43053ca0f0b3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867597570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.867597570 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_alert_test/latest

Test location	/workspace/coverage/default/24.kmac_app.956561898
Short name	T680
Test name
Test status
Simulation time	14297649140 ps
CPU time	311.4 seconds
Started	Jun 04 02:28:25 PM PDT 24
Finished	Jun 04 02:33:37 PM PDT 24
Peak memory	247820 kb
Host	smart-aa0f1661-d9ce-42eb-84b3-ad339bd76cdf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=956561898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.956561898 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_app/latest

Test location	/workspace/coverage/default/24.kmac_burst_write.104156774
Short name	T573
Test name
Test status
Simulation time	38737951374 ps
CPU time	442.03 seconds
Started	Jun 04 02:28:20 PM PDT 24
Finished	Jun 04 02:35:43 PM PDT 24
Peak memory	233792 kb
Host	smart-9a54f8fd-ff0a-4bc4-9726-8613b579cc93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=104156774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.104156774 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_burst_write/latest

Test location	/workspace/coverage/default/24.kmac_entropy_refresh.1824764155
Short name	T972
Test name
Test status
Simulation time	8446000286 ps
CPU time	318.47 seconds
Started	Jun 04 02:28:27 PM PDT 24
Finished	Jun 04 02:33:46 PM PDT 24
Peak memory	250032 kb
Host	smart-42cf338a-316f-4cc7-80e9-4f5025dd1f47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1824764155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.1824764155 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/24.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/24.kmac_error.1343841057
Short name	T802
Test name
Test status
Simulation time	9716958262 ps
CPU time	247.23 seconds
Started	Jun 04 02:28:26 PM PDT 24
Finished	Jun 04 02:32:34 PM PDT 24
Peak memory	252120 kb
Host	smart-71aa68ba-a47c-4448-a97f-a7344dcfa258
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1343841057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.1343841057 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_error/latest

Test location	/workspace/coverage/default/24.kmac_key_error.2169148186
Short name	T120
Test name
Test status
Simulation time	2984092605 ps
CPU time	7.79 seconds
Started	Jun 04 02:28:25 PM PDT 24
Finished	Jun 04 02:28:34 PM PDT 24
Peak memory	224544 kb
Host	smart-94eb824a-ff13-4aa1-b01b-03b30337fb64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2169148186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.2169148186 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_key_error/latest

Test location	/workspace/coverage/default/24.kmac_lc_escalation.1126244465
Short name	T804
Test name
Test status
Simulation time	82054459 ps
CPU time	1.4 seconds
Started	Jun 04 02:28:24 PM PDT 24
Finished	Jun 04 02:28:26 PM PDT 24
Peak memory	227216 kb
Host	smart-771e32f7-4fca-473e-a8fb-6aecf36e5b6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1126244465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.1126244465 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/24.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/24.kmac_long_msg_and_output.431884990
Short name	T359
Test name
Test status
Simulation time	27061701702 ps
CPU time	2160.73 seconds
Started	Jun 04 02:28:13 PM PDT 24
Finished	Jun 04 03:04:15 PM PDT 24
Peak memory	412916 kb
Host	smart-360ef199-7b9c-461d-a9d8-f3c4b1a7c8bd
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431884990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_an d_output.431884990 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/24.kmac_sideload.3970119533
Short name	T1051
Test name
Test status
Simulation time	7989998434 ps
CPU time	165.03 seconds
Started	Jun 04 02:28:20 PM PDT 24
Finished	Jun 04 02:31:06 PM PDT 24
Peak memory	238168 kb
Host	smart-10d12e04-13bd-4eea-b8f8-8aea7e6f9c67
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970119533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.3970119533 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_sideload/latest

Test location	/workspace/coverage/default/24.kmac_smoke.666717617
Short name	T627
Test name
Test status
Simulation time	259365777 ps
CPU time	5.68 seconds
Started	Jun 04 02:28:13 PM PDT 24
Finished	Jun 04 02:28:19 PM PDT 24
Peak memory	227232 kb
Host	smart-8d7f2003-c43d-44d2-a3ca-51f3724ba9b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=666717617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.666717617 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_smoke/latest

Test location	/workspace/coverage/default/24.kmac_stress_all.2364820923
Short name	T797
Test name
Test status
Simulation time	29094085870 ps
CPU time	764.8 seconds
Started	Jun 04 02:28:24 PM PDT 24
Finished	Jun 04 02:41:10 PM PDT 24
Peak memory	292372 kb
Host	smart-ecef54ce-f249-47d1-b835-78a9e1bae6cd
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2364820923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.2364820923 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_stress_all/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_kmac.854680611
Short name	T261
Test name
Test status
Simulation time	110190875 ps
CPU time	5.75 seconds
Started	Jun 04 02:28:27 PM PDT 24
Finished	Jun 04 02:28:33 PM PDT 24
Peak memory	220248 kb
Host	smart-d67951f1-ff48-4454-9117-f2ba371db2c8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854680611 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 24.kmac_test_vectors_kmac.854680611 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_kmac_xof.3138711053
Short name	T592
Test name
Test status
Simulation time	457071325 ps
CPU time	5.51 seconds
Started	Jun 04 02:28:28 PM PDT 24
Finished	Jun 04 02:28:34 PM PDT 24
Peak memory	220296 kb
Host	smart-eb63ec1a-e8dc-469f-8b27-7e8e68f2f87d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138711053 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_kmac_xof.3138711053 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_224.3167313989
Short name	T297
Test name
Test status
Simulation time	128734802702 ps
CPU time	2132.02 seconds
Started	Jun 04 02:28:18 PM PDT 24
Finished	Jun 04 03:03:52 PM PDT 24
Peak memory	391132 kb
Host	smart-590b25a2-30b7-40b6-9952-6648d0b9bf4b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3167313989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.3167313989 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_256.4205443759
Short name	T689
Test name
Test status
Simulation time	133980443068 ps
CPU time	1910.96 seconds
Started	Jun 04 02:28:20 PM PDT 24
Finished	Jun 04 03:00:12 PM PDT 24
Peak memory	397260 kb
Host	smart-9285511c-e789-4970-a5a5-8e656887052c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4205443759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.4205443759 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_384.1990964755
Short name	T871
Test name
Test status
Simulation time	49810021824 ps
CPU time	1815.33 seconds
Started	Jun 04 02:28:20 PM PDT 24
Finished	Jun 04 02:58:36 PM PDT 24
Peak memory	351128 kb
Host	smart-d69c5309-c32b-4a3e-9400-3b8360471fdb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1990964755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.1990964755 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_512.1903843895
Short name	T249
Test name
Test status
Simulation time	200993090363 ps
CPU time	1404.99 seconds
Started	Jun 04 02:28:19 PM PDT 24
Finished	Jun 04 02:51:46 PM PDT 24
Peak memory	297508 kb
Host	smart-4ade3cdd-8edd-415e-8d75-b8b626e4164d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1903843895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.1903843895 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_shake_128.735940806
Short name	T515
Test name
Test status
Simulation time	178529413578 ps
CPU time	5669.81 seconds
Started	Jun 04 02:28:18 PM PDT 24
Finished	Jun 04 04:02:49 PM PDT 24
Peak memory	652584 kb
Host	smart-c7c71ee5-7d31-4fb0-95f4-2cae7fc20bca
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=735940806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.735940806 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_shake_256.90048055
Short name	T913
Test name
Test status
Simulation time	70571021399 ps
CPU time	4970.35 seconds
Started	Jun 04 02:28:19 PM PDT 24
Finished	Jun 04 03:51:11 PM PDT 24
Peak memory	572664 kb
Host	smart-05ccdf44-ceb1-4d1c-b6ff-25615c674361
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=90048055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.90048055 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/25.kmac_alert_test.120719894
Short name	T1025
Test name
Test status
Simulation time	43951285 ps
CPU time	0.82 seconds
Started	Jun 04 02:28:53 PM PDT 24
Finished	Jun 04 02:28:54 PM PDT 24
Peak memory	218872 kb
Host	smart-c12098a0-b300-4d25-82cf-5739e38f7b8e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120719894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.120719894 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_alert_test/latest

Test location	/workspace/coverage/default/25.kmac_app.2978577420
Short name	T165
Test name
Test status
Simulation time	25774927817 ps
CPU time	118.21 seconds
Started	Jun 04 02:28:47 PM PDT 24
Finished	Jun 04 02:30:46 PM PDT 24
Peak memory	235788 kb
Host	smart-b3999334-49ba-417a-be27-4f01e100c9b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2978577420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.2978577420 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_app/latest

Test location	/workspace/coverage/default/25.kmac_burst_write.73990844
Short name	T601
Test name
Test status
Simulation time	11504594083 ps
CPU time	267.5 seconds
Started	Jun 04 02:28:39 PM PDT 24
Finished	Jun 04 02:33:07 PM PDT 24
Peak memory	230472 kb
Host	smart-b70467a8-59e2-4cf6-a8d2-9a4cad8856a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=73990844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.73990844 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_burst_write/latest

Test location	/workspace/coverage/default/25.kmac_entropy_refresh.204223870
Short name	T950
Test name
Test status
Simulation time	9365819193 ps
CPU time	64.16 seconds
Started	Jun 04 02:28:45 PM PDT 24
Finished	Jun 04 02:29:50 PM PDT 24
Peak memory	229896 kb
Host	smart-48d00c57-1a4c-4520-8de5-201761e3896c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=204223870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.204223870 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/25.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/25.kmac_error.1444135067
Short name	T619
Test name
Test status
Simulation time	110639637507 ps
CPU time	338.32 seconds
Started	Jun 04 02:28:47 PM PDT 24
Finished	Jun 04 02:34:26 PM PDT 24
Peak memory	260172 kb
Host	smart-4277d082-cf21-4cf8-8bdc-63eee99526a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1444135067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.1444135067 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_error/latest

Test location	/workspace/coverage/default/25.kmac_key_error.731864522
Short name	T407
Test name
Test status
Simulation time	3828062326 ps
CPU time	8.42 seconds
Started	Jun 04 02:28:53 PM PDT 24
Finished	Jun 04 02:29:03 PM PDT 24
Peak memory	224796 kb
Host	smart-2224f28e-c2a8-4745-b595-2f9b31a837c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=731864522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.731864522 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_key_error/latest

Test location	/workspace/coverage/default/25.kmac_lc_escalation.3130687658
Short name	T43
Test name
Test status
Simulation time	46909481 ps
CPU time	1.36 seconds
Started	Jun 04 02:28:53 PM PDT 24
Finished	Jun 04 02:28:55 PM PDT 24
Peak memory	227276 kb
Host	smart-a7af7baf-a2ea-49d9-9a28-4d60aa5e1ad6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130687658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.3130687658 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/25.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/25.kmac_long_msg_and_output.1401939842
Short name	T136
Test name
Test status
Simulation time	118370085768 ps
CPU time	3115.53 seconds
Started	Jun 04 02:28:38 PM PDT 24
Finished	Jun 04 03:20:34 PM PDT 24
Peak memory	462176 kb
Host	smart-64024142-7ac9-4ded-96c8-0161cce0f728
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401939842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a nd_output.1401939842 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/25.kmac_sideload.370612066
Short name	T621
Test name
Test status
Simulation time	7573909453 ps
CPU time	153.06 seconds
Started	Jun 04 02:28:39 PM PDT 24
Finished	Jun 04 02:31:12 PM PDT 24
Peak memory	243812 kb
Host	smart-83e5c06c-4d43-49f2-9d4b-2ad4e20a3d57
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370612066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.370612066 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_sideload/latest

Test location	/workspace/coverage/default/25.kmac_smoke.1670400049
Short name	T732
Test name
Test status
Simulation time	1842131851 ps
CPU time	46.5 seconds
Started	Jun 04 02:28:32 PM PDT 24
Finished	Jun 04 02:29:19 PM PDT 24
Peak memory	223412 kb
Host	smart-d983a48a-d2c8-4e0f-a919-a322260d54b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1670400049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1670400049 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_smoke/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_kmac.1533628922
Short name	T412
Test name
Test status
Simulation time	221395380 ps
CPU time	5.81 seconds
Started	Jun 04 02:28:47 PM PDT 24
Finished	Jun 04 02:28:53 PM PDT 24
Peak memory	219276 kb
Host	smart-43c9a1a9-68e7-4f59-9478-39c46109e712
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533628922 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.kmac_test_vectors_kmac.1533628922 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_kmac_xof.1194960412
Short name	T321
Test name
Test status
Simulation time	202089979 ps
CPU time	7.07 seconds
Started	Jun 04 02:28:46 PM PDT 24
Finished	Jun 04 02:28:54 PM PDT 24
Peak memory	219268 kb
Host	smart-3d700547-bea6-4ce3-b402-35969594557b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194960412 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_kmac_xof.1194960412 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_224.3201633665
Short name	T835
Test name
Test status
Simulation time	31439992714 ps
CPU time	1858.23 seconds
Started	Jun 04 02:28:38 PM PDT 24
Finished	Jun 04 02:59:37 PM PDT 24
Peak memory	403852 kb
Host	smart-1426d912-babf-49bb-b366-d313bbdc9a56
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3201633665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.3201633665 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_256.3051231533
Short name	T475
Test name
Test status
Simulation time	83095830712 ps
CPU time	1977.89 seconds
Started	Jun 04 02:28:39 PM PDT 24
Finished	Jun 04 03:01:37 PM PDT 24
Peak memory	391500 kb
Host	smart-d84e91a0-b27d-4a01-bc72-d0bd07604d48
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3051231533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.3051231533 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_384.463104238
Short name	T304
Test name
Test status
Simulation time	94148234094 ps
CPU time	1515.28 seconds
Started	Jun 04 02:28:39 PM PDT 24
Finished	Jun 04 02:53:55 PM PDT 24
Peak memory	344892 kb
Host	smart-0c78b53f-b047-4550-bd46-5a6da38357af
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=463104238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.463104238 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_512.1328868512
Short name	T579
Test name
Test status
Simulation time	104247831740 ps
CPU time	1216.45 seconds
Started	Jun 04 02:28:39 PM PDT 24
Finished	Jun 04 02:48:56 PM PDT 24
Peak memory	300800 kb
Host	smart-bbf96158-21e6-46ec-9511-3cf81e8e8d00
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1328868512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.1328868512 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_shake_128.763607029
Short name	T658
Test name
Test status
Simulation time	264329031551 ps
CPU time	6342.13 seconds
Started	Jun 04 02:28:47 PM PDT 24
Finished	Jun 04 04:14:30 PM PDT 24
Peak memory	671880 kb
Host	smart-1df953af-2034-4c84-b0e2-d5ac370af426
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=763607029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.763607029 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_shake_256.534718228
Short name	T657
Test name
Test status
Simulation time	55783758538 ps
CPU time	4637.9 seconds
Started	Jun 04 02:28:46 PM PDT 24
Finished	Jun 04 03:46:05 PM PDT 24
Peak memory	573788 kb
Host	smart-5ad9f8dd-70fb-417f-a5ac-c6b7e60ac4bc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=534718228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.534718228 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/26.kmac_alert_test.3751996345
Short name	T673
Test name
Test status
Simulation time	53830795 ps
CPU time	0.84 seconds
Started	Jun 04 02:29:16 PM PDT 24
Finished	Jun 04 02:29:17 PM PDT 24
Peak memory	218900 kb
Host	smart-e0906873-d16f-43ab-ad8a-e1fce014aa1e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751996345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.3751996345 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_alert_test/latest

Test location	/workspace/coverage/default/26.kmac_app.786153290
Short name	T571
Test name
Test status
Simulation time	86054689 ps
CPU time	4.33 seconds
Started	Jun 04 02:29:07 PM PDT 24
Finished	Jun 04 02:29:12 PM PDT 24
Peak memory	227320 kb
Host	smart-82ddaf18-5c1a-4585-9084-504e465473a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786153290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.786153290 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_app/latest

Test location	/workspace/coverage/default/26.kmac_burst_write.3893416847
Short name	T1075
Test name
Test status
Simulation time	63112467109 ps
CPU time	539.7 seconds
Started	Jun 04 02:28:59 PM PDT 24
Finished	Jun 04 02:37:59 PM PDT 24
Peak memory	236104 kb
Host	smart-df63593f-75ef-4b8b-b9d1-7529e90692f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3893416847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.3893416847 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_burst_write/latest

Test location	/workspace/coverage/default/26.kmac_entropy_refresh.219733170
Short name	T1045
Test name
Test status
Simulation time	16576522873 ps
CPU time	405.6 seconds
Started	Jun 04 02:29:06 PM PDT 24
Finished	Jun 04 02:35:52 PM PDT 24
Peak memory	253344 kb
Host	smart-0f68cdc2-0b8e-4378-ba52-ef2ca229899c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219733170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.219733170 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/26.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/26.kmac_error.1818128590
Short name	T810
Test name
Test status
Simulation time	18124756540 ps
CPU time	397.67 seconds
Started	Jun 04 02:29:05 PM PDT 24
Finished	Jun 04 02:35:44 PM PDT 24
Peak memory	259096 kb
Host	smart-c85a3d1f-4bc2-44e0-ad7a-40cbbd501d00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1818128590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1818128590 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_error/latest

Test location	/workspace/coverage/default/26.kmac_key_error.16109818
Short name	T591
Test name
Test status
Simulation time	2921021818 ps
CPU time	11.48 seconds
Started	Jun 04 02:29:07 PM PDT 24
Finished	Jun 04 02:29:19 PM PDT 24
Peak memory	225928 kb
Host	smart-b526ad66-f7cf-4ace-a838-3c569dc190d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=16109818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.16109818 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_key_error/latest

Test location	/workspace/coverage/default/26.kmac_lc_escalation.1301445789
Short name	T480
Test name
Test status
Simulation time	50940260 ps
CPU time	1.33 seconds
Started	Jun 04 02:29:14 PM PDT 24
Finished	Jun 04 02:29:16 PM PDT 24
Peak memory	219288 kb
Host	smart-3903073f-98c5-40b2-8a3f-f5e139243601
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1301445789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.1301445789 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/26.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/26.kmac_long_msg_and_output.1121479011
Short name	T332
Test name
Test status
Simulation time	22628138430 ps
CPU time	2493.41 seconds
Started	Jun 04 02:28:53 PM PDT 24
Finished	Jun 04 03:10:28 PM PDT 24
Peak memory	421008 kb
Host	smart-09c12b3c-7cbd-41ce-9f3d-fe30e1f9b47c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121479011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a nd_output.1121479011 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/26.kmac_sideload.1618429329
Short name	T35
Test name
Test status
Simulation time	10597457356 ps
CPU time	277.41 seconds
Started	Jun 04 02:28:53 PM PDT 24
Finished	Jun 04 02:33:31 PM PDT 24
Peak memory	243400 kb
Host	smart-80ac0bc9-fd61-4781-8328-6f9a4f4e9bbe
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618429329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1618429329 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_sideload/latest

Test location	/workspace/coverage/default/26.kmac_smoke.2634277575
Short name	T254
Test name
Test status
Simulation time	5026991498 ps
CPU time	18.42 seconds
Started	Jun 04 02:28:53 PM PDT 24
Finished	Jun 04 02:29:13 PM PDT 24
Peak memory	222960 kb
Host	smart-7ef07921-9974-4865-8321-2da915d7f0de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2634277575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.2634277575 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_smoke/latest

Test location	/workspace/coverage/default/26.kmac_stress_all.3750117015
Short name	T70
Test name
Test status
Simulation time	70777217513 ps
CPU time	883.67 seconds
Started	Jun 04 02:29:17 PM PDT 24
Finished	Jun 04 02:44:01 PM PDT 24
Peak memory	313608 kb
Host	smart-bbf3cad6-e8a0-4d70-8ba8-4bf063db0998
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3750117015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.3750117015 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_stress_all/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_kmac.2402789437
Short name	T34
Test name
Test status
Simulation time	825700701 ps
CPU time	5.58 seconds
Started	Jun 04 02:29:08 PM PDT 24
Finished	Jun 04 02:29:14 PM PDT 24
Peak memory	219236 kb
Host	smart-08b48eb3-9be3-496e-bdbd-6c573680cfb8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402789437 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.kmac_test_vectors_kmac.2402789437 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_kmac_xof.1579643016
Short name	T1048
Test name
Test status
Simulation time	437965568 ps
CPU time	5.77 seconds
Started	Jun 04 02:29:06 PM PDT 24
Finished	Jun 04 02:29:12 PM PDT 24
Peak memory	219352 kb
Host	smart-3838f90d-7100-4333-a593-4762bbe202e8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579643016 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_kmac_xof.1579643016 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_224.2365055364
Short name	T589
Test name
Test status
Simulation time	396051629469 ps
CPU time	2164.22 seconds
Started	Jun 04 02:28:59 PM PDT 24
Finished	Jun 04 03:05:04 PM PDT 24
Peak memory	389868 kb
Host	smart-cf0d34b8-dfc6-4140-a21a-bff7f73e78ce
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2365055364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.2365055364 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_256.25561332
Short name	T942
Test name
Test status
Simulation time	64103164982 ps
CPU time	2052.18 seconds
Started	Jun 04 02:29:00 PM PDT 24
Finished	Jun 04 03:03:13 PM PDT 24
Peak memory	386024 kb
Host	smart-c539b857-7ed3-4c7c-97a1-e69b2a9063f5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=25561332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.25561332 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_384.4134708535
Short name	T826
Test name
Test status
Simulation time	14578068481 ps
CPU time	1562.39 seconds
Started	Jun 04 02:29:00 PM PDT 24
Finished	Jun 04 02:55:03 PM PDT 24
Peak memory	338456 kb
Host	smart-606a51c2-566c-486a-adb2-270f26424b03
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4134708535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.4134708535 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_shake_128.75027567
Short name	T750
Test name
Test status
Simulation time	1084425023662 ps
CPU time	6546.61 seconds
Started	Jun 04 02:29:00 PM PDT 24
Finished	Jun 04 04:18:08 PM PDT 24
Peak memory	658312 kb
Host	smart-9a661e40-01d4-4dd4-a1cd-6350acd82b70
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=75027567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.75027567 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/27.kmac_alert_test.1360429204
Short name	T414
Test name
Test status
Simulation time	42783653 ps
CPU time	0.8 seconds
Started	Jun 04 02:29:34 PM PDT 24
Finished	Jun 04 02:29:35 PM PDT 24
Peak memory	218924 kb
Host	smart-f6d6c715-0232-45cb-b439-29f520e7a0b9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360429204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.1360429204 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_alert_test/latest

Test location	/workspace/coverage/default/27.kmac_app.1994249726
Short name	T827
Test name
Test status
Simulation time	10181020407 ps
CPU time	147.12 seconds
Started	Jun 04 02:29:27 PM PDT 24
Finished	Jun 04 02:31:54 PM PDT 24
Peak memory	238436 kb
Host	smart-71df72f4-c7d8-43f2-9196-16353732ce04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994249726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.1994249726 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_app/latest

Test location	/workspace/coverage/default/27.kmac_burst_write.3260632989
Short name	T343
Test name
Test status
Simulation time	58439460057 ps
CPU time	701.41 seconds
Started	Jun 04 02:29:16 PM PDT 24
Finished	Jun 04 02:40:58 PM PDT 24
Peak memory	235404 kb
Host	smart-721f64bb-5043-481a-af1d-6fe2454f8b32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3260632989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.3260632989 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_burst_write/latest

Test location	/workspace/coverage/default/27.kmac_entropy_refresh.1419789343
Short name	T72
Test name
Test status
Simulation time	5567309274 ps
CPU time	131.82 seconds
Started	Jun 04 02:29:34 PM PDT 24
Finished	Jun 04 02:31:47 PM PDT 24
Peak memory	236520 kb
Host	smart-b521873a-8027-4b83-857d-da592c80cf7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1419789343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.1419789343 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/27.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/27.kmac_error.4096468554
Short name	T979
Test name
Test status
Simulation time	1577188459 ps
CPU time	124.92 seconds
Started	Jun 04 02:29:38 PM PDT 24
Finished	Jun 04 02:31:43 PM PDT 24
Peak memory	242972 kb
Host	smart-ba359a62-5a96-4f14-9be4-b0b6cb034372
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4096468554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.4096468554 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_error/latest

Test location	/workspace/coverage/default/27.kmac_key_error.2591063462
Short name	T122
Test name
Test status
Simulation time	4352734426 ps
CPU time	6.43 seconds
Started	Jun 04 02:29:35 PM PDT 24
Finished	Jun 04 02:29:42 PM PDT 24
Peak memory	224616 kb
Host	smart-a59a4679-230d-4ea2-a5be-7f84ffcc2bcb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591063462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.2591063462 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_key_error/latest

Test location	/workspace/coverage/default/27.kmac_long_msg_and_output.1139037447
Short name	T418
Test name
Test status
Simulation time	335400146321 ps
CPU time	2907.15 seconds
Started	Jun 04 02:29:14 PM PDT 24
Finished	Jun 04 03:17:42 PM PDT 24
Peak memory	446580 kb
Host	smart-7a3543fc-5225-4fee-ab74-4959edd55c1d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139037447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a nd_output.1139037447 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/27.kmac_sideload.3575402624
Short name	T1026
Test name
Test status
Simulation time	6512605719 ps
CPU time	158.07 seconds
Started	Jun 04 02:29:13 PM PDT 24
Finished	Jun 04 02:31:51 PM PDT 24
Peak memory	238860 kb
Host	smart-226c52a5-358d-4aeb-9ce1-7cd2ffb4c553
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575402624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.3575402624 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_sideload/latest

Test location	/workspace/coverage/default/27.kmac_smoke.2032038135
Short name	T677
Test name
Test status
Simulation time	5471144286 ps
CPU time	61.15 seconds
Started	Jun 04 02:29:14 PM PDT 24
Finished	Jun 04 02:30:16 PM PDT 24
Peak memory	220764 kb
Host	smart-4d8a43bf-3401-4ce0-b4d9-2f24222f49c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032038135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.2032038135 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_smoke/latest

Test location	/workspace/coverage/default/27.kmac_stress_all.1795233896
Short name	T494
Test name
Test status
Simulation time	5373612602 ps
CPU time	361.73 seconds
Started	Jun 04 02:29:38 PM PDT 24
Finished	Jun 04 02:35:40 PM PDT 24
Peak memory	274208 kb
Host	smart-3d287457-0419-47d9-b768-4a5244113669
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1795233896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.1795233896 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_stress_all/latest

Test location	/workspace/coverage/default/27.kmac_stress_all_with_rand_reset.1134339294
Short name	T965
Test name
Test status
Simulation time	19750361006 ps
CPU time	812.37 seconds
Started	Jun 04 02:29:33 PM PDT 24
Finished	Jun 04 02:43:06 PM PDT 24
Peak memory	285280 kb
Host	smart-a0824805-432a-4c55-852d-4a6bb3c76fb0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1134339294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all_with_rand_reset.1134339294 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_kmac.766412325
Short name	T728
Test name
Test status
Simulation time	445529664 ps
CPU time	6.32 seconds
Started	Jun 04 02:29:19 PM PDT 24
Finished	Jun 04 02:29:26 PM PDT 24
Peak memory	219344 kb
Host	smart-0adc4b06-dd2a-41d1-a5c5-c184a9caf222
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766412325 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 27.kmac_test_vectors_kmac.766412325 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_kmac_xof.3079970787
Short name	T851
Test name
Test status
Simulation time	384496055 ps
CPU time	5.87 seconds
Started	Jun 04 02:29:28 PM PDT 24
Finished	Jun 04 02:29:34 PM PDT 24
Peak memory	220236 kb
Host	smart-7ebf12de-5b0b-41cb-b14b-3711cf1f1268
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079970787 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_kmac_xof.3079970787 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_224.195909736
Short name	T691
Test name
Test status
Simulation time	88353374315 ps
CPU time	1934.86 seconds
Started	Jun 04 02:29:13 PM PDT 24
Finished	Jun 04 03:01:29 PM PDT 24
Peak memory	401932 kb
Host	smart-ff724929-25c7-4d4e-b418-7889ae0bf08e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=195909736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.195909736 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_256.3405158618
Short name	T486
Test name
Test status
Simulation time	80752514585 ps
CPU time	2144.5 seconds
Started	Jun 04 02:29:14 PM PDT 24
Finished	Jun 04 03:05:00 PM PDT 24
Peak memory	384988 kb
Host	smart-e4dc2593-7b56-4dcb-b163-bda94006532d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3405158618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.3405158618 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_384.1842127079
Short name	T427
Test name
Test status
Simulation time	60121131876 ps
CPU time	1445.66 seconds
Started	Jun 04 02:29:20 PM PDT 24
Finished	Jun 04 02:53:27 PM PDT 24
Peak memory	340364 kb
Host	smart-45db92ce-1e3c-4b0f-93e5-d5d474c70abe
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1842127079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.1842127079 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_512.4078560602
Short name	T299
Test name
Test status
Simulation time	69520072071 ps
CPU time	1356.52 seconds
Started	Jun 04 02:29:20 PM PDT 24
Finished	Jun 04 02:51:57 PM PDT 24
Peak memory	300536 kb
Host	smart-52010216-99f6-4322-97ed-4c3528abae0a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4078560602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.4078560602 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_shake_128.1289298904
Short name	T914
Test name
Test status
Simulation time	181963477157 ps
CPU time	5917.91 seconds
Started	Jun 04 02:29:20 PM PDT 24
Finished	Jun 04 04:07:59 PM PDT 24
Peak memory	646972 kb
Host	smart-1b6ba8af-6d62-43bd-abe0-2db6b1e8dd64
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1289298904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.1289298904 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_shake_256.854903511
Short name	T1056
Test name
Test status
Simulation time	1000902472184 ps
CPU time	5592.15 seconds
Started	Jun 04 02:29:22 PM PDT 24
Finished	Jun 04 04:02:36 PM PDT 24
Peak memory	574748 kb
Host	smart-a15343a7-7380-4d43-93a1-ab1c6c55943c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=854903511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.854903511 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/28.kmac_alert_test.1576068374
Short name	T466
Test name
Test status
Simulation time	63389117 ps
CPU time	0.85 seconds
Started	Jun 04 02:30:39 PM PDT 24
Finished	Jun 04 02:30:40 PM PDT 24
Peak memory	219060 kb
Host	smart-08672cb8-477d-46e8-8e2b-0ee4add8cd20
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576068374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.1576068374 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_alert_test/latest

Test location	/workspace/coverage/default/28.kmac_app.1850834505
Short name	T105
Test name
Test status
Simulation time	11526019515 ps
CPU time	362.39 seconds
Started	Jun 04 02:29:58 PM PDT 24
Finished	Jun 04 02:36:01 PM PDT 24
Peak memory	251924 kb
Host	smart-f4d99f1f-deae-43e0-b687-a626aa78cd11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1850834505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.1850834505 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_app/latest

Test location	/workspace/coverage/default/28.kmac_burst_write.3152722300
Short name	T1000
Test name
Test status
Simulation time	18292129186 ps
CPU time	1344.91 seconds
Started	Jun 04 02:29:43 PM PDT 24
Finished	Jun 04 02:52:08 PM PDT 24
Peak memory	243804 kb
Host	smart-660cef8d-acfd-45a2-93f0-fe7568af1d52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3152722300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.3152722300 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_burst_write/latest

Test location	/workspace/coverage/default/28.kmac_entropy_refresh.2530030964
Short name	T872
Test name
Test status
Simulation time	6491687066 ps
CPU time	208.61 seconds
Started	Jun 04 02:29:59 PM PDT 24
Finished	Jun 04 02:33:28 PM PDT 24
Peak memory	244756 kb
Host	smart-0aab7f1e-a3a7-4502-9812-b52bf0f73fd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2530030964 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.2530030964 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/28.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/28.kmac_error.1764081075
Short name	T160
Test name
Test status
Simulation time	57466994776 ps
CPU time	435.14 seconds
Started	Jun 04 02:29:58 PM PDT 24
Finished	Jun 04 02:37:14 PM PDT 24
Peak memory	268312 kb
Host	smart-323654d7-b5cc-4395-950a-9465f9d75dcc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764081075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1764081075 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_error/latest

Test location	/workspace/coverage/default/28.kmac_key_error.1683065635
Short name	T388
Test name
Test status
Simulation time	5703788032 ps
CPU time	4.82 seconds
Started	Jun 04 02:29:56 PM PDT 24
Finished	Jun 04 02:30:02 PM PDT 24
Peak memory	223884 kb
Host	smart-0fad419d-5615-4780-9418-de649d67cf57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1683065635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1683065635 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_key_error/latest

Test location	/workspace/coverage/default/28.kmac_lc_escalation.3226103414
Short name	T970
Test name
Test status
Simulation time	170542536 ps
CPU time	1.51 seconds
Started	Jun 04 02:29:57 PM PDT 24
Finished	Jun 04 02:29:59 PM PDT 24
Peak memory	227284 kb
Host	smart-cbb17c5d-82db-4d9d-89a7-8ca8c3dc542b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226103414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.3226103414 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/28.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/28.kmac_long_msg_and_output.1799746751
Short name	T664
Test name
Test status
Simulation time	83026593736 ps
CPU time	2982.9 seconds
Started	Jun 04 02:29:41 PM PDT 24
Finished	Jun 04 03:19:24 PM PDT 24
Peak memory	456576 kb
Host	smart-8cd979af-769c-49b6-a61c-22281cf1b017
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799746751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a nd_output.1799746751 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/28.kmac_sideload.3823021942
Short name	T295
Test name
Test status
Simulation time	6134225111 ps
CPU time	37.58 seconds
Started	Jun 04 02:29:42 PM PDT 24
Finished	Jun 04 02:30:20 PM PDT 24
Peak memory	227512 kb
Host	smart-f9a092b9-2c98-4027-b16a-68de58d8a3ad
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823021942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.3823021942 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_sideload/latest

Test location	/workspace/coverage/default/28.kmac_smoke.1988920816
Short name	T572
Test name
Test status
Simulation time	806741664 ps
CPU time	4.99 seconds
Started	Jun 04 02:29:41 PM PDT 24
Finished	Jun 04 02:29:47 PM PDT 24
Peak memory	222204 kb
Host	smart-1d8accbe-1540-490c-9e03-087e05490660
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1988920816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.1988920816 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_smoke/latest

Test location	/workspace/coverage/default/28.kmac_stress_all.2819548945
Short name	T781
Test name
Test status
Simulation time	142673385259 ps
CPU time	1283.75 seconds
Started	Jun 04 02:29:57 PM PDT 24
Finished	Jun 04 02:51:22 PM PDT 24
Peak memory	355144 kb
Host	smart-de847ade-8e47-4010-82d8-95f201d49cb4
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2819548945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.2819548945 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_stress_all/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_kmac.1759502776
Short name	T845
Test name
Test status
Simulation time	131458000 ps
CPU time	6.11 seconds
Started	Jun 04 02:29:58 PM PDT 24
Finished	Jun 04 02:30:04 PM PDT 24
Peak memory	220256 kb
Host	smart-427a169a-3d52-4199-8b22-b830cdba2186
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759502776 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 28.kmac_test_vectors_kmac.1759502776 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_kmac_xof.523589995
Short name	T506
Test name
Test status
Simulation time	1205486926 ps
CPU time	6.17 seconds
Started	Jun 04 02:29:57 PM PDT 24
Finished	Jun 04 02:30:04 PM PDT 24
Peak memory	219312 kb
Host	smart-671b67f1-19af-4631-8581-06a6df564b42
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523589995 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 28.kmac_test_vectors_kmac_xof.523589995 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_224.2671302368
Short name	T458
Test name
Test status
Simulation time	99671857209 ps
CPU time	1917.43 seconds
Started	Jun 04 02:29:50 PM PDT 24
Finished	Jun 04 03:01:48 PM PDT 24
Peak memory	402924 kb
Host	smart-27b91f76-8558-461d-a873-710ee8ba135f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2671302368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.2671302368 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_256.2056953010
Short name	T599
Test name
Test status
Simulation time	67429680247 ps
CPU time	1960.07 seconds
Started	Jun 04 02:29:48 PM PDT 24
Finished	Jun 04 03:02:29 PM PDT 24
Peak memory	379920 kb
Host	smart-db33d994-a18a-4a61-9cff-a409ba51053f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2056953010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.2056953010 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_384.3060851174
Short name	T508
Test name
Test status
Simulation time	49781610620 ps
CPU time	1744.94 seconds
Started	Jun 04 02:29:57 PM PDT 24
Finished	Jun 04 02:59:03 PM PDT 24
Peak memory	339424 kb
Host	smart-4eacb16c-8275-4f7b-aacf-5501724bf0bb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3060851174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.3060851174 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_512.186528030
Short name	T792
Test name
Test status
Simulation time	32505479633 ps
CPU time	1107.37 seconds
Started	Jun 04 02:29:56 PM PDT 24
Finished	Jun 04 02:48:24 PM PDT 24
Peak memory	294968 kb
Host	smart-f95aa174-51de-4d4e-96b6-9af151d81bd4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=186528030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.186528030 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_shake_128.2891293407
Short name	T925
Test name
Test status
Simulation time	116620802279 ps
CPU time	5291.81 seconds
Started	Jun 04 02:29:57 PM PDT 24
Finished	Jun 04 03:58:10 PM PDT 24
Peak memory	650624 kb
Host	smart-c66f9354-1152-4cdb-9e07-4eca1b65dc0e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2891293407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.2891293407 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_shake_256.1307172655
Short name	T756
Test name
Test status
Simulation time	757568808855 ps
CPU time	5238.9 seconds
Started	Jun 04 02:29:58 PM PDT 24
Finished	Jun 04 03:57:18 PM PDT 24
Peak memory	565928 kb
Host	smart-41071e96-bcf0-40d6-8a6e-2e252b06b4d5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1307172655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.1307172655 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/29.kmac_alert_test.2511981886
Short name	T593
Test name
Test status
Simulation time	29215812 ps
CPU time	0.81 seconds
Started	Jun 04 02:30:34 PM PDT 24
Finished	Jun 04 02:30:35 PM PDT 24
Peak memory	218948 kb
Host	smart-a091c749-0a75-4dcd-b619-b6bc5d25ec95
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511981886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.2511981886 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_alert_test/latest

Test location	/workspace/coverage/default/29.kmac_app.1908001570
Short name	T292
Test name
Test status
Simulation time	612819407 ps
CPU time	17.54 seconds
Started	Jun 04 02:30:21 PM PDT 24
Finished	Jun 04 02:30:39 PM PDT 24
Peak memory	227316 kb
Host	smart-aa9cef69-0e1b-482f-8332-d9e0b3af5763
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1908001570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1908001570 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_app/latest

Test location	/workspace/coverage/default/29.kmac_burst_write.1937059879
Short name	T471
Test name
Test status
Simulation time	11318559065 ps
CPU time	347.48 seconds
Started	Jun 04 02:30:12 PM PDT 24
Finished	Jun 04 02:36:00 PM PDT 24
Peak memory	230928 kb
Host	smart-dfe1f2c0-6baa-4194-b7f3-f44d2ae15d51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1937059879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.1937059879 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_burst_write/latest

Test location	/workspace/coverage/default/29.kmac_entropy_refresh.3322286113
Short name	T404
Test name
Test status
Simulation time	7836369665 ps
CPU time	262.78 seconds
Started	Jun 04 02:30:24 PM PDT 24
Finished	Jun 04 02:34:47 PM PDT 24
Peak memory	246188 kb
Host	smart-5969f8c7-1e60-49be-a5f2-201f3074ea37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3322286113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.3322286113 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/29.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/29.kmac_error.1529776525
Short name	T1013
Test name
Test status
Simulation time	17477985650 ps
CPU time	439.67 seconds
Started	Jun 04 02:30:30 PM PDT 24
Finished	Jun 04 02:37:50 PM PDT 24
Peak memory	256412 kb
Host	smart-99a461cb-9ae0-47f6-8ba7-78d9cc89d254
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1529776525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.1529776525 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_error/latest

Test location	/workspace/coverage/default/29.kmac_key_error.3520478039
Short name	T477
Test name
Test status
Simulation time	167238587 ps
CPU time	1.91 seconds
Started	Jun 04 02:30:30 PM PDT 24
Finished	Jun 04 02:30:33 PM PDT 24
Peak memory	223072 kb
Host	smart-0c920013-fc2c-40f1-b57d-a720b0936443
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3520478039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3520478039 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_key_error/latest

Test location	/workspace/coverage/default/29.kmac_lc_escalation.2862778352
Short name	T474
Test name
Test status
Simulation time	60341271 ps
CPU time	1.55 seconds
Started	Jun 04 02:30:31 PM PDT 24
Finished	Jun 04 02:30:33 PM PDT 24
Peak memory	227200 kb
Host	smart-d845b35d-5faf-49e7-bb82-940af9187cf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2862778352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.2862778352 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/29.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/29.kmac_long_msg_and_output.3888649672
Short name	T324
Test name
Test status
Simulation time	97625246285 ps
CPU time	2599.76 seconds
Started	Jun 04 02:30:08 PM PDT 24
Finished	Jun 04 03:13:28 PM PDT 24
Peak memory	417668 kb
Host	smart-f4ee5980-c7d1-483d-978d-40c92595f8b3
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888649672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a nd_output.3888649672 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/29.kmac_sideload.2659972465
Short name	T944
Test name
Test status
Simulation time	8848730328 ps
CPU time	206.23 seconds
Started	Jun 04 02:30:14 PM PDT 24
Finished	Jun 04 02:33:41 PM PDT 24
Peak memory	240108 kb
Host	smart-89a07696-d9a8-4ca8-933d-bfcfe9604cb5
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659972465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.2659972465 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_sideload/latest

Test location	/workspace/coverage/default/29.kmac_smoke.2906320732
Short name	T915
Test name
Test status
Simulation time	6964828822 ps
CPU time	63.81 seconds
Started	Jun 04 02:30:07 PM PDT 24
Finished	Jun 04 02:31:12 PM PDT 24
Peak memory	227428 kb
Host	smart-7d6bd2e9-3956-440d-855e-943222eeb86f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2906320732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.2906320732 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_smoke/latest

Test location	/workspace/coverage/default/29.kmac_stress_all.2706890267
Short name	T57
Test name
Test status
Simulation time	50066296185 ps
CPU time	2167.04 seconds
Started	Jun 04 02:30:27 PM PDT 24
Finished	Jun 04 03:06:34 PM PDT 24
Peak memory	391676 kb
Host	smart-96bec8e7-a0bc-4412-bd34-75072beb78d8
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2706890267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.2706890267 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_stress_all/latest

Test location	/workspace/coverage/default/29.kmac_stress_all_with_rand_reset.2875034194
Short name	T567
Test name
Test status
Simulation time	68756908085 ps
CPU time	900.76 seconds
Started	Jun 04 02:30:36 PM PDT 24
Finished	Jun 04 02:45:37 PM PDT 24
Peak memory	325828 kb
Host	smart-bc8c32a4-ba2b-4a91-a441-737fc563c7a2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2875034194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all_with_rand_reset.2875034194 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_kmac.169178731
Short name	T241
Test name
Test status
Simulation time	369221534 ps
CPU time	6.64 seconds
Started	Jun 04 02:30:22 PM PDT 24
Finished	Jun 04 02:30:29 PM PDT 24
Peak memory	219368 kb
Host	smart-7d142a9a-6316-4699-8b8c-0aabca883ee6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169178731 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 29.kmac_test_vectors_kmac.169178731 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_kmac_xof.2835576241
Short name	T1067
Test name
Test status
Simulation time	1006677491 ps
CPU time	7.05 seconds
Started	Jun 04 02:30:23 PM PDT 24
Finished	Jun 04 02:30:30 PM PDT 24
Peak memory	219336 kb
Host	smart-776cbd4e-ada7-41a8-ba0b-265e97c0aa4d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835576241 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_kmac_xof.2835576241 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_256.773131257
Short name	T110
Test name
Test status
Simulation time	62805093227 ps
CPU time	1926.05 seconds
Started	Jun 04 02:30:11 PM PDT 24
Finished	Jun 04 03:02:18 PM PDT 24
Peak memory	387292 kb
Host	smart-9a8d182d-3600-4866-911b-8c6df1f06a3d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=773131257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.773131257 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_384.4258920974
Short name	T1076
Test name
Test status
Simulation time	61841800494 ps
CPU time	1684.85 seconds
Started	Jun 04 02:30:14 PM PDT 24
Finished	Jun 04 02:58:20 PM PDT 24
Peak memory	342968 kb
Host	smart-d664c4c1-b4ab-4f16-963c-eb934cd8a2ac
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4258920974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.4258920974 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_512.2466305271
Short name	T784
Test name
Test status
Simulation time	34878702672 ps
CPU time	1328.36 seconds
Started	Jun 04 02:30:14 PM PDT 24
Finished	Jun 04 02:52:23 PM PDT 24
Peak memory	302884 kb
Host	smart-f0dea298-b355-4bf7-90cf-2258e891eb36
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2466305271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.2466305271 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_shake_128.3574886127
Short name	T1031
Test name
Test status
Simulation time	1610873732910 ps
CPU time	6531.85 seconds
Started	Jun 04 02:30:24 PM PDT 24
Finished	Jun 04 04:19:17 PM PDT 24
Peak memory	655112 kb
Host	smart-d89eca68-bc9c-45cd-9c68-3d1c045c735d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3574886127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.3574886127 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_shake_256.1568024516
Short name	T378
Test name
Test status
Simulation time	1140848340626 ps
CPU time	4729.87 seconds
Started	Jun 04 02:30:22 PM PDT 24
Finished	Jun 04 03:49:13 PM PDT 24
Peak memory	559608 kb
Host	smart-75939508-e88f-4e29-8605-bf87b42678dc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1568024516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.1568024516 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/3.kmac_alert_test.134790081
Short name	T916
Test name
Test status
Simulation time	40606831 ps
CPU time	0.84 seconds
Started	Jun 04 02:23:43 PM PDT 24
Finished	Jun 04 02:23:44 PM PDT 24
Peak memory	218944 kb
Host	smart-5e7522a4-5750-40e1-ba58-facf0a8f631e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134790081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.134790081 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_alert_test/latest

Test location	/workspace/coverage/default/3.kmac_app.3340071613
Short name	T964
Test name
Test status
Simulation time	36327349807 ps
CPU time	208.03 seconds
Started	Jun 04 02:23:38 PM PDT 24
Finished	Jun 04 02:27:06 PM PDT 24
Peak memory	242080 kb
Host	smart-fe03bc99-400f-43a1-8626-bee082eb7204
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3340071613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3340071613 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_app/latest

Test location	/workspace/coverage/default/3.kmac_app_with_partial_data.162974413
Short name	T990
Test name
Test status
Simulation time	8329703098 ps
CPU time	386.9 seconds
Started	Jun 04 02:23:39 PM PDT 24
Finished	Jun 04 02:30:06 PM PDT 24
Peak memory	252864 kb
Host	smart-0576b036-cb51-4548-8ff3-c9c21fd88868
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=162974413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.162974413 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/3.kmac_burst_write.3162085528
Short name	T374
Test name
Test status
Simulation time	10129445917 ps
CPU time	785.51 seconds
Started	Jun 04 02:23:37 PM PDT 24
Finished	Jun 04 02:36:43 PM PDT 24
Peak memory	235836 kb
Host	smart-e27414db-edd5-428e-96f2-fd5aa8a00bcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3162085528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3162085528 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_burst_write/latest

Test location	/workspace/coverage/default/3.kmac_edn_timeout_error.4184981725
Short name	T864
Test name
Test status
Simulation time	37496242 ps
CPU time	1.12 seconds
Started	Jun 04 02:23:47 PM PDT 24
Finished	Jun 04 02:23:49 PM PDT 24
Peak memory	219120 kb
Host	smart-72486ab8-1528-4325-942b-6962f89e2f8d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4184981725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.4184981725 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_mode_error.1390028994
Short name	T194
Test name
Test status
Simulation time	453352787 ps
CPU time	39.1 seconds
Started	Jun 04 02:23:51 PM PDT 24
Finished	Jun 04 02:24:30 PM PDT 24
Peak memory	227208 kb
Host	smart-90ca6a09-9030-4682-972b-4c720df2e7e8
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1390028994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.1390028994 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_ready_error.2276045496
Short name	T687
Test name
Test status
Simulation time	5364032959 ps
CPU time	30.88 seconds
Started	Jun 04 02:23:41 PM PDT 24
Finished	Jun 04 02:24:13 PM PDT 24
Peak memory	227404 kb
Host	smart-d9c368d6-9e08-4c82-8746-e695507710c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2276045496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2276045496 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/3.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_refresh.2086008334
Short name	T37
Test name
Test status
Simulation time	6898098694 ps
CPU time	178.12 seconds
Started	Jun 04 02:23:39 PM PDT 24
Finished	Jun 04 02:26:38 PM PDT 24
Peak memory	243880 kb
Host	smart-c672c9a7-a145-489c-866a-906142e0c39b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2086008334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.2086008334 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/3.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/3.kmac_error.3973015557
Short name	T158
Test name
Test status
Simulation time	10216126630 ps
CPU time	396.71 seconds
Started	Jun 04 02:23:37 PM PDT 24
Finished	Jun 04 02:30:14 PM PDT 24
Peak memory	260140 kb
Host	smart-3bc6ba68-3019-411e-888d-08e767b8d4b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3973015557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.3973015557 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_error/latest

Test location	/workspace/coverage/default/3.kmac_key_error.1965993194
Short name	T774
Test name
Test status
Simulation time	24752507719 ps
CPU time	11.21 seconds
Started	Jun 04 02:23:40 PM PDT 24
Finished	Jun 04 02:23:51 PM PDT 24
Peak memory	225356 kb
Host	smart-78c1129a-da76-4f3e-b35f-c5abc68abaf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1965993194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1965993194 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_key_error/latest

Test location	/workspace/coverage/default/3.kmac_lc_escalation.753754273
Short name	T46
Test name
Test status
Simulation time	42817345 ps
CPU time	1.45 seconds
Started	Jun 04 02:23:52 PM PDT 24
Finished	Jun 04 02:23:54 PM PDT 24
Peak memory	227320 kb
Host	smart-23c534c2-167e-4344-9c1b-2936da2de56e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=753754273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.753754273 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/3.kmac_long_msg_and_output.3449538656
Short name	T532
Test name
Test status
Simulation time	223910436122 ps
CPU time	2832.53 seconds
Started	Jun 04 02:23:37 PM PDT 24
Finished	Jun 04 03:10:50 PM PDT 24
Peak memory	445800 kb
Host	smart-04b80d42-a66c-4e7c-9d61-acbae742efa6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449538656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an d_output.3449538656 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/3.kmac_mubi.1329903871
Short name	T546
Test name
Test status
Simulation time	192599693403 ps
CPU time	239.49 seconds
Started	Jun 04 02:23:37 PM PDT 24
Finished	Jun 04 02:27:38 PM PDT 24
Peak memory	245560 kb
Host	smart-ce1e4269-11ad-4544-a122-e1941abb4299
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1329903871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.1329903871 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_mubi/latest

Test location	/workspace/coverage/default/3.kmac_sec_cm.2321468343
Short name	T28
Test name
Test status
Simulation time	28504006545 ps
CPU time	105.18 seconds
Started	Jun 04 02:23:52 PM PDT 24
Finished	Jun 04 02:25:38 PM PDT 24
Peak memory	278556 kb
Host	smart-7c15669c-19a7-48e4-ad23-b2bebb88d495
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321468343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.2321468343 +enable_maski ng=1 +sw_key_masked=0
Directory	/workspace/3.kmac_sec_cm/latest

Test location	/workspace/coverage/default/3.kmac_sideload.2870476501
Short name	T421
Test name
Test status
Simulation time	2801464129 ps
CPU time	195.43 seconds
Started	Jun 04 02:23:39 PM PDT 24
Finished	Jun 04 02:26:55 PM PDT 24
Peak memory	241084 kb
Host	smart-5bc90193-89b3-40eb-b2ab-632089645b92
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870476501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.2870476501 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_sideload/latest

Test location	/workspace/coverage/default/3.kmac_smoke.3006285991
Short name	T743
Test name
Test status
Simulation time	3951487881 ps
CPU time	27.28 seconds
Started	Jun 04 02:23:36 PM PDT 24
Finished	Jun 04 02:24:04 PM PDT 24
Peak memory	227436 kb
Host	smart-8e001531-0a0a-4f70-8129-767c1650fd37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3006285991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.3006285991 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_smoke/latest

Test location	/workspace/coverage/default/3.kmac_stress_all.2487690144
Short name	T51
Test name
Test status
Simulation time	176776064554 ps
CPU time	1104.02 seconds
Started	Jun 04 02:23:52 PM PDT 24
Finished	Jun 04 02:42:17 PM PDT 24
Peak memory	353616 kb
Host	smart-b89f8fb5-a874-4a20-8441-ab3536ebd84d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2487690144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.2487690144 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_stress_all/latest

Test location	/workspace/coverage/default/3.kmac_stress_all_with_rand_reset.1507236258
Short name	T135
Test name
Test status
Simulation time	72536938562 ps
CPU time	2843.75 seconds
Started	Jun 04 02:23:54 PM PDT 24
Finished	Jun 04 03:11:18 PM PDT 24
Peak memory	421408 kb
Host	smart-e75e6e56-735e-4742-a41b-fdffb4be45d6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1507236258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_rand_reset.1507236258 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_kmac.3322050003
Short name	T203
Test name
Test status
Simulation time	305124570 ps
CPU time	5.42 seconds
Started	Jun 04 02:23:37 PM PDT 24
Finished	Jun 04 02:23:43 PM PDT 24
Peak memory	219324 kb
Host	smart-0e08011c-aee3-4ead-80b7-b1d5e0d65299
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322050003 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.kmac_test_vectors_kmac.3322050003 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_kmac_xof.453340311
Short name	T1065
Test name
Test status
Simulation time	136820654 ps
CPU time	5.21 seconds
Started	Jun 04 02:23:35 PM PDT 24
Finished	Jun 04 02:23:41 PM PDT 24
Peak memory	219272 kb
Host	smart-90d5340a-1d4e-4b36-b20a-2cf626d9b9f6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453340311 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.kmac_test_vectors_kmac_xof.453340311 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_224.2131288709
Short name	T762
Test name
Test status
Simulation time	97443205805 ps
CPU time	1990.11 seconds
Started	Jun 04 02:23:35 PM PDT 24
Finished	Jun 04 02:56:46 PM PDT 24
Peak memory	398480 kb
Host	smart-e38f8269-f6a3-4a56-ba27-e68552c94e8d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2131288709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.2131288709 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_256.3643167969
Short name	T765
Test name
Test status
Simulation time	37895488025 ps
CPU time	1858.88 seconds
Started	Jun 04 02:23:41 PM PDT 24
Finished	Jun 04 02:54:41 PM PDT 24
Peak memory	379720 kb
Host	smart-7495e6c6-1eae-4819-83dd-27edc501f52a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3643167969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3643167969 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_384.3612354991
Short name	T524
Test name
Test status
Simulation time	16808745621 ps
CPU time	1558.87 seconds
Started	Jun 04 02:23:42 PM PDT 24
Finished	Jun 04 02:49:41 PM PDT 24
Peak memory	344120 kb
Host	smart-da7405c5-0c5c-4123-90a7-ae6e4bf5be9e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3612354991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3612354991 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_512.3943902088
Short name	T569
Test name
Test status
Simulation time	93434835096 ps
CPU time	1155.25 seconds
Started	Jun 04 02:23:41 PM PDT 24
Finished	Jun 04 02:42:57 PM PDT 24
Peak memory	296120 kb
Host	smart-65118cea-7920-405d-a464-f4c6d9102687
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3943902088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.3943902088 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_shake_128.847696880
Short name	T554
Test name
Test status
Simulation time	1044189874452 ps
CPU time	6146.45 seconds
Started	Jun 04 02:23:36 PM PDT 24
Finished	Jun 04 04:06:04 PM PDT 24
Peak memory	658084 kb
Host	smart-44c43f47-f7f0-471d-9efc-42c62814818f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=847696880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.847696880 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_shake_256.2165903631
Short name	T945
Test name
Test status
Simulation time	218647014381 ps
CPU time	4712.02 seconds
Started	Jun 04 02:23:37 PM PDT 24
Finished	Jun 04 03:42:11 PM PDT 24
Peak memory	564344 kb
Host	smart-fdba91a1-f78b-4f3e-b19e-ef5c22197da2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2165903631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.2165903631 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/30.kmac_alert_test.4276111766
Short name	T704
Test name
Test status
Simulation time	33565115 ps
CPU time	0.86 seconds
Started	Jun 04 02:31:06 PM PDT 24
Finished	Jun 04 02:31:08 PM PDT 24
Peak memory	218960 kb
Host	smart-5d6276d3-cb49-47c3-a91b-0568ab1c417b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276111766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.4276111766 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_alert_test/latest

Test location	/workspace/coverage/default/30.kmac_app.4005514486
Short name	T819
Test name
Test status
Simulation time	13301427276 ps
CPU time	309.45 seconds
Started	Jun 04 02:30:59 PM PDT 24
Finished	Jun 04 02:36:09 PM PDT 24
Peak memory	246780 kb
Host	smart-eb136ef5-50f5-4c13-97bd-3e5231f483e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4005514486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.4005514486 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_app/latest

Test location	/workspace/coverage/default/30.kmac_burst_write.491299043
Short name	T344
Test name
Test status
Simulation time	9704153367 ps
CPU time	1056.69 seconds
Started	Jun 04 02:30:45 PM PDT 24
Finished	Jun 04 02:48:22 PM PDT 24
Peak memory	237000 kb
Host	smart-cc9d2ef8-00ca-436a-ab17-88f78747df04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=491299043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.491299043 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_burst_write/latest

Test location	/workspace/coverage/default/30.kmac_entropy_refresh.114455538
Short name	T283
Test name
Test status
Simulation time	13630443448 ps
CPU time	171.64 seconds
Started	Jun 04 02:31:01 PM PDT 24
Finished	Jun 04 02:33:53 PM PDT 24
Peak memory	239880 kb
Host	smart-ff3d0004-01c3-4c50-8003-d190be11d053
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114455538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.114455538 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/30.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/30.kmac_error.1013261392
Short name	T933
Test name
Test status
Simulation time	11114096955 ps
CPU time	171.47 seconds
Started	Jun 04 02:30:58 PM PDT 24
Finished	Jun 04 02:33:50 PM PDT 24
Peak memory	252004 kb
Host	smart-13fb6c66-1a73-431c-821e-5928df725ca2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1013261392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.1013261392 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_error/latest

Test location	/workspace/coverage/default/30.kmac_key_error.189228033
Short name	T267
Test name
Test status
Simulation time	759868495 ps
CPU time	5.9 seconds
Started	Jun 04 02:30:58 PM PDT 24
Finished	Jun 04 02:31:04 PM PDT 24
Peak memory	223788 kb
Host	smart-8fe05504-99af-48e4-9df1-da1b790b90d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=189228033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.189228033 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_key_error/latest

Test location	/workspace/coverage/default/30.kmac_lc_escalation.3019247983
Short name	T919
Test name
Test status
Simulation time	154258309 ps
CPU time	1.5 seconds
Started	Jun 04 02:30:57 PM PDT 24
Finished	Jun 04 02:30:59 PM PDT 24
Peak memory	227376 kb
Host	smart-3c8ae1e4-4801-42b1-9a81-03b2f7245b2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3019247983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.3019247983 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/30.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/30.kmac_long_msg_and_output.1034664878
Short name	T651
Test name
Test status
Simulation time	59859594054 ps
CPU time	1465.64 seconds
Started	Jun 04 02:30:36 PM PDT 24
Finished	Jun 04 02:55:02 PM PDT 24
Peak memory	359404 kb
Host	smart-0edb6bdd-27bf-46bf-9011-fb83c6a5b941
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034664878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a nd_output.1034664878 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/30.kmac_sideload.658331599
Short name	T337
Test name
Test status
Simulation time	70669178720 ps
CPU time	255.28 seconds
Started	Jun 04 02:30:35 PM PDT 24
Finished	Jun 04 02:34:51 PM PDT 24
Peak memory	244132 kb
Host	smart-4ae83599-b2ce-4872-8a68-3c7fdea35f4b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658331599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.658331599 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_sideload/latest

Test location	/workspace/coverage/default/30.kmac_smoke.2148937643
Short name	T1042
Test name
Test status
Simulation time	5981163651 ps
CPU time	34.45 seconds
Started	Jun 04 02:30:37 PM PDT 24
Finished	Jun 04 02:31:11 PM PDT 24
Peak memory	219348 kb
Host	smart-d527567a-6d61-463b-8b85-e45bf9997d81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148937643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2148937643 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_smoke/latest

Test location	/workspace/coverage/default/30.kmac_stress_all.4178732476
Short name	T156
Test name
Test status
Simulation time	325813413071 ps
CPU time	1672.62 seconds
Started	Jun 04 02:31:07 PM PDT 24
Finished	Jun 04 02:59:01 PM PDT 24
Peak memory	358580 kb
Host	smart-fb994705-a0d0-490d-8a6f-ab0f703f8488
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4178732476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.4178732476 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_stress_all/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_kmac.3956141519
Short name	T997
Test name
Test status
Simulation time	924117590 ps
CPU time	6.54 seconds
Started	Jun 04 02:30:50 PM PDT 24
Finished	Jun 04 02:30:57 PM PDT 24
Peak memory	220196 kb
Host	smart-f14e7f28-d76d-42f4-91ea-b452b33b019d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956141519 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 30.kmac_test_vectors_kmac.3956141519 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_kmac_xof.2758645354
Short name	T815
Test name
Test status
Simulation time	1303897687 ps
CPU time	6.63 seconds
Started	Jun 04 02:30:51 PM PDT 24
Finished	Jun 04 02:30:58 PM PDT 24
Peak memory	219292 kb
Host	smart-6c92de1b-0421-44a2-be2b-ef263a43f8bb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758645354 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_kmac_xof.2758645354 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_224.2444944500
Short name	T582
Test name
Test status
Simulation time	185950401155 ps
CPU time	2173.1 seconds
Started	Jun 04 02:30:42 PM PDT 24
Finished	Jun 04 03:06:56 PM PDT 24
Peak memory	393688 kb
Host	smart-c5c1eb6d-e483-4bc1-a278-f4bfebee2076
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2444944500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.2444944500 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_256.1095700949
Short name	T456
Test name
Test status
Simulation time	620005323168 ps
CPU time	2367.05 seconds
Started	Jun 04 02:30:42 PM PDT 24
Finished	Jun 04 03:10:10 PM PDT 24
Peak memory	390052 kb
Host	smart-aea7cc3c-0637-4da2-9632-b8ade2398b0e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1095700949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.1095700949 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_384.3062588359
Short name	T331
Test name
Test status
Simulation time	48410484939 ps
CPU time	1827.08 seconds
Started	Jun 04 02:30:43 PM PDT 24
Finished	Jun 04 03:01:11 PM PDT 24
Peak memory	341232 kb
Host	smart-b676e7b1-4ea0-47f9-b899-40f97417a0e3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3062588359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.3062588359 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_512.980424943
Short name	T661
Test name
Test status
Simulation time	290009707963 ps
CPU time	1416.42 seconds
Started	Jun 04 02:30:42 PM PDT 24
Finished	Jun 04 02:54:19 PM PDT 24
Peak memory	302648 kb
Host	smart-af8f368e-eac6-411b-a163-ac8c74038916
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=980424943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.980424943 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_shake_128.33766491
Short name	T246
Test name
Test status
Simulation time	182768369835 ps
CPU time	5720.09 seconds
Started	Jun 04 02:30:49 PM PDT 24
Finished	Jun 04 04:06:11 PM PDT 24
Peak memory	648796 kb
Host	smart-107389b9-50af-4f6e-9222-542a55c586e4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=33766491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.33766491 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_shake_256.578087526
Short name	T943
Test name
Test status
Simulation time	287462441988 ps
CPU time	5162.91 seconds
Started	Jun 04 02:30:50 PM PDT 24
Finished	Jun 04 03:56:54 PM PDT 24
Peak memory	568580 kb
Host	smart-5ebd73ec-5be6-4238-aba1-73ca9ae26975
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=578087526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.578087526 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/31.kmac_alert_test.2867181371
Short name	T333
Test name
Test status
Simulation time	33349628 ps
CPU time	0.81 seconds
Started	Jun 04 02:31:21 PM PDT 24
Finished	Jun 04 02:31:22 PM PDT 24
Peak memory	218912 kb
Host	smart-61a00ef4-644d-4a43-9897-e57d73f7fb12
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867181371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.2867181371 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_alert_test/latest

Test location	/workspace/coverage/default/31.kmac_app.1814458616
Short name	T154
Test name
Test status
Simulation time	7852684583 ps
CPU time	307.6 seconds
Started	Jun 04 02:31:16 PM PDT 24
Finished	Jun 04 02:36:24 PM PDT 24
Peak memory	250036 kb
Host	smart-e50c5170-54d1-4314-8856-9ce4bf7aacc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814458616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.1814458616 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_app/latest

Test location	/workspace/coverage/default/31.kmac_burst_write.1000650008
Short name	T545
Test name
Test status
Simulation time	14471515209 ps
CPU time	592.54 seconds
Started	Jun 04 02:31:31 PM PDT 24
Finished	Jun 04 02:41:24 PM PDT 24
Peak memory	234644 kb
Host	smart-1cb7939e-ec37-4ab3-9c12-d0dd0c6b5dda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1000650008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.1000650008 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_burst_write/latest

Test location	/workspace/coverage/default/31.kmac_entropy_refresh.3747801716
Short name	T843
Test name
Test status
Simulation time	902178593 ps
CPU time	24.92 seconds
Started	Jun 04 02:31:17 PM PDT 24
Finished	Jun 04 02:31:43 PM PDT 24
Peak memory	227356 kb
Host	smart-c8eb86e6-ea79-4a0b-aee7-b48585252af6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3747801716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.3747801716 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/31.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/31.kmac_error.3105036472
Short name	T23
Test name
Test status
Simulation time	11758916176 ps
CPU time	465.08 seconds
Started	Jun 04 02:31:14 PM PDT 24
Finished	Jun 04 02:39:00 PM PDT 24
Peak memory	268424 kb
Host	smart-6cba35b5-02ab-4dd4-813a-e1d8fce49463
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3105036472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.3105036472 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_error/latest

Test location	/workspace/coverage/default/31.kmac_key_error.2809752082
Short name	T641
Test name
Test status
Simulation time	1607553920 ps
CPU time	3.78 seconds
Started	Jun 04 02:31:22 PM PDT 24
Finished	Jun 04 02:31:26 PM PDT 24
Peak memory	223784 kb
Host	smart-9909afdc-598e-412e-8293-1d847a22ccd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2809752082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.2809752082 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_key_error/latest

Test location	/workspace/coverage/default/31.kmac_lc_escalation.4171318223
Short name	T41
Test name
Test status
Simulation time	236695194 ps
CPU time	1.36 seconds
Started	Jun 04 02:31:22 PM PDT 24
Finished	Jun 04 02:31:24 PM PDT 24
Peak memory	227260 kb
Host	smart-b9b77243-2c7f-4a69-87ec-2b3c19a8041f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4171318223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.4171318223 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/31.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/31.kmac_long_msg_and_output.3304101160
Short name	T538
Test name
Test status
Simulation time	464504213154 ps
CPU time	2586.16 seconds
Started	Jun 04 02:31:14 PM PDT 24
Finished	Jun 04 03:14:21 PM PDT 24
Peak memory	437608 kb
Host	smart-9a317da7-941d-413f-9134-6798bdf3c534
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304101160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a nd_output.3304101160 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/31.kmac_sideload.3859882813
Short name	T3
Test name
Test status
Simulation time	42903494639 ps
CPU time	257.08 seconds
Started	Jun 04 02:31:15 PM PDT 24
Finished	Jun 04 02:35:32 PM PDT 24
Peak memory	243688 kb
Host	smart-4d4a891a-9b48-46b7-a23a-4f6ddbfdc905
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859882813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.3859882813 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_sideload/latest

Test location	/workspace/coverage/default/31.kmac_smoke.3296978370
Short name	T366
Test name
Test status
Simulation time	1626557939 ps
CPU time	55.75 seconds
Started	Jun 04 02:31:07 PM PDT 24
Finished	Jun 04 02:32:03 PM PDT 24
Peak memory	227384 kb
Host	smart-09161d66-520c-4bc0-b189-7458a489b65c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3296978370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.3296978370 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_smoke/latest

Test location	/workspace/coverage/default/31.kmac_stress_all.2523063466
Short name	T71
Test name
Test status
Simulation time	68697127402 ps
CPU time	1866.86 seconds
Started	Jun 04 02:31:25 PM PDT 24
Finished	Jun 04 03:02:32 PM PDT 24
Peak memory	399808 kb
Host	smart-26490927-1492-49c5-b0e3-5c3b8619ebec
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2523063466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.2523063466 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_stress_all/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_kmac.926386174
Short name	T415
Test name
Test status
Simulation time	947343174 ps
CPU time	6.33 seconds
Started	Jun 04 02:31:13 PM PDT 24
Finished	Jun 04 02:31:20 PM PDT 24
Peak memory	219316 kb
Host	smart-d477fd5f-834a-4ab6-8b78-dcbcbfa92ae8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926386174 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 31.kmac_test_vectors_kmac.926386174 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_kmac_xof.1404458279
Short name	T282
Test name
Test status
Simulation time	1020475615 ps
CPU time	6.95 seconds
Started	Jun 04 02:31:17 PM PDT 24
Finished	Jun 04 02:31:24 PM PDT 24
Peak memory	220200 kb
Host	smart-b5f81e0c-07fe-4ba6-a41b-9c5d441e82a1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404458279 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_kmac_xof.1404458279 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_224.4288172440
Short name	T534
Test name
Test status
Simulation time	251114963426 ps
CPU time	2268.43 seconds
Started	Jun 04 02:31:14 PM PDT 24
Finished	Jun 04 03:09:03 PM PDT 24
Peak memory	401976 kb
Host	smart-f2e3db52-b33e-4a1e-8150-db278af840f9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4288172440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.4288172440 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_256.3698940028
Short name	T1033
Test name
Test status
Simulation time	164237952406 ps
CPU time	2067.07 seconds
Started	Jun 04 02:31:15 PM PDT 24
Finished	Jun 04 03:05:42 PM PDT 24
Peak memory	384024 kb
Host	smart-8d634de5-ac22-46bf-aeb6-294440ff5acc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3698940028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.3698940028 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_384.3547169962
Short name	T124
Test name
Test status
Simulation time	256571734734 ps
CPU time	1595.82 seconds
Started	Jun 04 02:31:13 PM PDT 24
Finished	Jun 04 02:57:50 PM PDT 24
Peak memory	342604 kb
Host	smart-a9390a41-c60d-4072-94e1-b4e8b042ee3d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3547169962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.3547169962 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_512.2494466260
Short name	T917
Test name
Test status
Simulation time	409497748868 ps
CPU time	1202.26 seconds
Started	Jun 04 02:31:14 PM PDT 24
Finished	Jun 04 02:51:17 PM PDT 24
Peak memory	298864 kb
Host	smart-1a9a686c-c158-45bf-be0a-a06845d95d17
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2494466260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.2494466260 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_shake_128.2619029178
Short name	T1066
Test name
Test status
Simulation time	738023269663 ps
CPU time	5918.33 seconds
Started	Jun 04 02:31:17 PM PDT 24
Finished	Jun 04 04:09:57 PM PDT 24
Peak memory	654436 kb
Host	smart-8191d058-f722-4a4f-8041-c583a48c11bd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2619029178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.2619029178 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_shake_256.2753179118
Short name	T714
Test name
Test status
Simulation time	914083076366 ps
CPU time	5488.55 seconds
Started	Jun 04 02:31:14 PM PDT 24
Finished	Jun 04 04:02:44 PM PDT 24
Peak memory	569676 kb
Host	smart-f512b321-4563-4a87-829f-f17aa73b7a4a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2753179118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.2753179118 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/32.kmac_alert_test.1978347803
Short name	T305
Test name
Test status
Simulation time	19068533 ps
CPU time	0.9 seconds
Started	Jun 04 02:31:50 PM PDT 24
Finished	Jun 04 02:31:52 PM PDT 24
Peak memory	218916 kb
Host	smart-30dcde34-915b-4afb-a85f-a6148ebff938
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978347803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.1978347803 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_alert_test/latest

Test location	/workspace/coverage/default/32.kmac_app.1036666644
Short name	T881
Test name
Test status
Simulation time	31823779690 ps
CPU time	286.08 seconds
Started	Jun 04 02:31:39 PM PDT 24
Finished	Jun 04 02:36:26 PM PDT 24
Peak memory	249840 kb
Host	smart-f749cfe6-bfda-4925-9988-4486be902538
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1036666644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.1036666644 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_app/latest

Test location	/workspace/coverage/default/32.kmac_burst_write.1851337195
Short name	T960
Test name
Test status
Simulation time	50303726303 ps
CPU time	986.65 seconds
Started	Jun 04 02:31:22 PM PDT 24
Finished	Jun 04 02:47:49 PM PDT 24
Peak memory	239040 kb
Host	smart-e13276e8-02d2-4b75-9bf2-760b24588251
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851337195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.1851337195 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_burst_write/latest

Test location	/workspace/coverage/default/32.kmac_entropy_refresh.2542248441
Short name	T533
Test name
Test status
Simulation time	41447180056 ps
CPU time	189.49 seconds
Started	Jun 04 02:31:36 PM PDT 24
Finished	Jun 04 02:34:46 PM PDT 24
Peak memory	239496 kb
Host	smart-81f3a116-05de-4503-a99e-ac5e914b8f8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542248441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.2542248441 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/32.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/32.kmac_error.56655422
Short name	T1039
Test name
Test status
Simulation time	17513041482 ps
CPU time	283.17 seconds
Started	Jun 04 02:31:45 PM PDT 24
Finished	Jun 04 02:36:28 PM PDT 24
Peak memory	256772 kb
Host	smart-722c0e89-ba95-4d23-81f7-f28f390b85bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56655422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.56655422 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_error/latest

Test location	/workspace/coverage/default/32.kmac_key_error.751578381
Short name	T1035
Test name
Test status
Simulation time	213944227 ps
CPU time	2.55 seconds
Started	Jun 04 02:31:47 PM PDT 24
Finished	Jun 04 02:31:50 PM PDT 24
Peak memory	223340 kb
Host	smart-a09bc6d3-d530-42a4-9b5d-56ca74b07f22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=751578381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.751578381 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_key_error/latest

Test location	/workspace/coverage/default/32.kmac_lc_escalation.3574863310
Short name	T45
Test name
Test status
Simulation time	56090924 ps
CPU time	1.54 seconds
Started	Jun 04 02:31:47 PM PDT 24
Finished	Jun 04 02:31:49 PM PDT 24
Peak memory	227312 kb
Host	smart-1909eb09-25a0-400d-8beb-5f0d73c11914
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574863310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.3574863310 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/32.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/32.kmac_long_msg_and_output.1713047179
Short name	T895
Test name
Test status
Simulation time	110077948335 ps
CPU time	477.37 seconds
Started	Jun 04 02:31:23 PM PDT 24
Finished	Jun 04 02:39:21 PM PDT 24
Peak memory	255056 kb
Host	smart-bc0c2942-18cd-453a-9841-337cfdd230a3
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713047179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a nd_output.1713047179 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/32.kmac_sideload.1393387918
Short name	T189
Test name
Test status
Simulation time	1981626741 ps
CPU time	29.3 seconds
Started	Jun 04 02:31:22 PM PDT 24
Finished	Jun 04 02:31:52 PM PDT 24
Peak memory	224444 kb
Host	smart-5b707f97-d46c-4b2a-ae98-e94d236426bf
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393387918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1393387918 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_sideload/latest

Test location	/workspace/coverage/default/32.kmac_smoke.459490496
Short name	T442
Test name
Test status
Simulation time	6829470470 ps
CPU time	78.89 seconds
Started	Jun 04 02:31:22 PM PDT 24
Finished	Jun 04 02:32:41 PM PDT 24
Peak memory	227468 kb
Host	smart-396a80f5-241f-4b52-8284-b2dcfd9ccc8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459490496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.459490496 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_smoke/latest

Test location	/workspace/coverage/default/32.kmac_stress_all.1797851287
Short name	T833
Test name
Test status
Simulation time	18602474555 ps
CPU time	681.47 seconds
Started	Jun 04 02:31:47 PM PDT 24
Finished	Jun 04 02:43:09 PM PDT 24
Peak memory	334036 kb
Host	smart-20dd4e56-37d6-4e3d-b8d2-49f9892be841
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1797851287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.1797851287 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_stress_all/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_kmac.942099618
Short name	T924
Test name
Test status
Simulation time	512294185 ps
CPU time	6.17 seconds
Started	Jun 04 02:31:37 PM PDT 24
Finished	Jun 04 02:31:44 PM PDT 24
Peak memory	219296 kb
Host	smart-273834cc-a0e7-44fd-afbd-6bcbc8e87311
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942099618 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 32.kmac_test_vectors_kmac.942099618 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_kmac_xof.2862068843
Short name	T112
Test name
Test status
Simulation time	97671678 ps
CPU time	5.93 seconds
Started	Jun 04 02:31:38 PM PDT 24
Finished	Jun 04 02:31:44 PM PDT 24
Peak memory	219256 kb
Host	smart-eeb1223b-d358-4a1d-b56f-db3eea3b3c4c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862068843 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_kmac_xof.2862068843 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_224.822367348
Short name	T451
Test name
Test status
Simulation time	41401057336 ps
CPU time	1942.68 seconds
Started	Jun 04 02:31:30 PM PDT 24
Finished	Jun 04 03:03:54 PM PDT 24
Peak memory	395032 kb
Host	smart-6ad6a8e2-7abe-4a3f-9ee2-24c8e5a14205
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=822367348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.822367348 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_256.2507076556
Short name	T729
Test name
Test status
Simulation time	39332551927 ps
CPU time	1899.08 seconds
Started	Jun 04 02:31:29 PM PDT 24
Finished	Jun 04 03:03:09 PM PDT 24
Peak memory	390244 kb
Host	smart-b8ba59ab-592d-48c4-8941-b35dbc2f2a93
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2507076556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.2507076556 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_384.3000983375
Short name	T322
Test name
Test status
Simulation time	296691891931 ps
CPU time	1860.71 seconds
Started	Jun 04 02:31:28 PM PDT 24
Finished	Jun 04 03:02:30 PM PDT 24
Peak memory	344524 kb
Host	smart-0d6c945b-3748-445d-a0de-7d258ef4c8c9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3000983375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.3000983375 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_512.2529514710
Short name	T757
Test name
Test status
Simulation time	468546940683 ps
CPU time	1386.87 seconds
Started	Jun 04 02:31:30 PM PDT 24
Finished	Jun 04 02:54:37 PM PDT 24
Peak memory	299768 kb
Host	smart-176e8d72-add0-40f2-a527-f5ee6aa021ae
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2529514710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.2529514710 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_shake_128.3167012649
Short name	T193
Test name
Test status
Simulation time	393214485555 ps
CPU time	5617.89 seconds
Started	Jun 04 02:31:28 PM PDT 24
Finished	Jun 04 04:05:07 PM PDT 24
Peak memory	662188 kb
Host	smart-036f82ab-3c93-4558-af56-45cb0821c3cc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3167012649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.3167012649 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_shake_256.978534607
Short name	T672
Test name
Test status
Simulation time	83284208981 ps
CPU time	4818.14 seconds
Started	Jun 04 02:31:38 PM PDT 24
Finished	Jun 04 03:51:57 PM PDT 24
Peak memory	571548 kb
Host	smart-1a9a6ed2-b38b-42e8-bdd8-b85cf0fdbea5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=978534607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.978534607 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/33.kmac_alert_test.4230174376
Short name	T693
Test name
Test status
Simulation time	16537092 ps
CPU time	0.83 seconds
Started	Jun 04 02:32:13 PM PDT 24
Finished	Jun 04 02:32:15 PM PDT 24
Peak memory	218944 kb
Host	smart-03c73f4b-ad73-47d8-9651-d5b76ae3a2ea
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230174376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.4230174376 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_alert_test/latest

Test location	/workspace/coverage/default/33.kmac_app.3921005654
Short name	T1029
Test name
Test status
Simulation time	6946195011 ps
CPU time	30.08 seconds
Started	Jun 04 02:32:06 PM PDT 24
Finished	Jun 04 02:32:37 PM PDT 24
Peak memory	227544 kb
Host	smart-f3c5b0b2-98f3-430a-81e7-b50cac671449
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3921005654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.3921005654 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_app/latest

Test location	/workspace/coverage/default/33.kmac_burst_write.1044690160
Short name	T394
Test name
Test status
Simulation time	13533956019 ps
CPU time	1314.67 seconds
Started	Jun 04 02:31:49 PM PDT 24
Finished	Jun 04 02:53:44 PM PDT 24
Peak memory	243904 kb
Host	smart-a5631ba8-2f9d-43e3-89d0-44132917ef51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1044690160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.1044690160 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_burst_write/latest

Test location	/workspace/coverage/default/33.kmac_entropy_refresh.1845734852
Short name	T735
Test name
Test status
Simulation time	3902352111 ps
CPU time	199.31 seconds
Started	Jun 04 02:32:09 PM PDT 24
Finished	Jun 04 02:35:29 PM PDT 24
Peak memory	240392 kb
Host	smart-60b7be4e-0b43-4504-927a-23c5800ff3d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1845734852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1845734852 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/33.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/33.kmac_error.1531437004
Short name	T818
Test name
Test status
Simulation time	5479062283 ps
CPU time	238.85 seconds
Started	Jun 04 02:32:08 PM PDT 24
Finished	Jun 04 02:36:07 PM PDT 24
Peak memory	255568 kb
Host	smart-3205bd43-c898-480f-9c57-ef121927b632
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1531437004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.1531437004 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_error/latest

Test location	/workspace/coverage/default/33.kmac_key_error.343019771
Short name	T936
Test name
Test status
Simulation time	2198263856 ps
CPU time	5.57 seconds
Started	Jun 04 02:32:06 PM PDT 24
Finished	Jun 04 02:32:12 PM PDT 24
Peak memory	223700 kb
Host	smart-7b8feb69-eeaf-4db8-b777-44b7845609af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=343019771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.343019771 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_key_error/latest

Test location	/workspace/coverage/default/33.kmac_lc_escalation.2750187517
Short name	T25
Test name
Test status
Simulation time	48245259 ps
CPU time	1.39 seconds
Started	Jun 04 02:32:13 PM PDT 24
Finished	Jun 04 02:32:15 PM PDT 24
Peak memory	227388 kb
Host	smart-97d6710c-fd24-42a1-a078-1b55e19d01c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2750187517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.2750187517 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/33.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/33.kmac_long_msg_and_output.3658827214
Short name	T457
Test name
Test status
Simulation time	19634953885 ps
CPU time	2048.57 seconds
Started	Jun 04 02:31:50 PM PDT 24
Finished	Jun 04 03:05:59 PM PDT 24
Peak memory	405876 kb
Host	smart-4f8f2fa2-3544-4455-9de9-565962504e80
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658827214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a nd_output.3658827214 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/33.kmac_sideload.881225106
Short name	T287
Test name
Test status
Simulation time	7903676888 ps
CPU time	185.83 seconds
Started	Jun 04 02:31:52 PM PDT 24
Finished	Jun 04 02:34:59 PM PDT 24
Peak memory	237556 kb
Host	smart-f5531afb-2d55-47ed-8970-2e6127f9be40
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881225106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.881225106 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_sideload/latest

Test location	/workspace/coverage/default/33.kmac_smoke.1096605188
Short name	T405
Test name
Test status
Simulation time	12142690685 ps
CPU time	65.58 seconds
Started	Jun 04 02:31:49 PM PDT 24
Finished	Jun 04 02:32:56 PM PDT 24
Peak memory	226396 kb
Host	smart-71be1d07-7f05-42ab-9ebb-2e55b76c984b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1096605188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.1096605188 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_smoke/latest

Test location	/workspace/coverage/default/33.kmac_stress_all.174037253
Short name	T777
Test name
Test status
Simulation time	71772441615 ps
CPU time	1462.37 seconds
Started	Jun 04 02:32:15 PM PDT 24
Finished	Jun 04 02:56:38 PM PDT 24
Peak memory	321800 kb
Host	smart-b5e8826f-0a5a-4047-bbff-0f1d1241a2f8
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=174037253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.174037253 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_stress_all/latest

Test location	/workspace/coverage/default/33.kmac_stress_all_with_rand_reset.2762793873
Short name	T55
Test name
Test status
Simulation time	57567307998 ps
CPU time	2623.37 seconds
Started	Jun 04 02:32:13 PM PDT 24
Finished	Jun 04 03:15:57 PM PDT 24
Peak memory	433720 kb
Host	smart-f35ecc9c-9b8f-4d12-81db-e3798a148663
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2762793873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all_with_rand_reset.2762793873 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_kmac.3255654891
Short name	T225
Test name
Test status
Simulation time	287976781 ps
CPU time	5.72 seconds
Started	Jun 04 02:32:06 PM PDT 24
Finished	Jun 04 02:32:13 PM PDT 24
Peak memory	219276 kb
Host	smart-34ee7127-f691-4b7f-9c56-c88c5d369311
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255654891 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 33.kmac_test_vectors_kmac.3255654891 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_kmac_xof.1029225367
Short name	T930
Test name
Test status
Simulation time	2041832248 ps
CPU time	6.86 seconds
Started	Jun 04 02:32:07 PM PDT 24
Finished	Jun 04 02:32:14 PM PDT 24
Peak memory	219308 kb
Host	smart-8cba2c40-51b2-4e14-a493-beb42ca2eb1f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029225367 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_kmac_xof.1029225367 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_224.163843830
Short name	T652
Test name
Test status
Simulation time	25137570272 ps
CPU time	1797.92 seconds
Started	Jun 04 02:31:58 PM PDT 24
Finished	Jun 04 03:01:57 PM PDT 24
Peak memory	395328 kb
Host	smart-fdb37128-2dd0-4155-ba11-5b7483ce93da
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=163843830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.163843830 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_256.4270611458
Short name	T1084
Test name
Test status
Simulation time	44414988271 ps
CPU time	1953.88 seconds
Started	Jun 04 02:31:59 PM PDT 24
Finished	Jun 04 03:04:34 PM PDT 24
Peak memory	395784 kb
Host	smart-1d965724-c433-4e49-9eed-9956962e52a1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4270611458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.4270611458 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_384.2871160333
Short name	T1062
Test name
Test status
Simulation time	15759190416 ps
CPU time	1572.83 seconds
Started	Jun 04 02:31:59 PM PDT 24
Finished	Jun 04 02:58:12 PM PDT 24
Peak memory	336644 kb
Host	smart-4505c4d0-0abd-4c8e-942d-c2aabf1ebfd6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2871160333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.2871160333 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_512.2648650836
Short name	T155
Test name
Test status
Simulation time	63529913291 ps
CPU time	1247.68 seconds
Started	Jun 04 02:32:06 PM PDT 24
Finished	Jun 04 02:52:55 PM PDT 24
Peak memory	301780 kb
Host	smart-67481e63-0fce-4ac7-b1a5-4cf959682006
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2648650836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.2648650836 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_shake_128.2244248162
Short name	T390
Test name
Test status
Simulation time	84026764421 ps
CPU time	5334.58 seconds
Started	Jun 04 02:32:07 PM PDT 24
Finished	Jun 04 04:01:03 PM PDT 24
Peak memory	663976 kb
Host	smart-01b0ffac-4502-485d-8eaa-002fc436a79c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2244248162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.2244248162 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_shake_256.2569922893
Short name	T399
Test name
Test status
Simulation time	414326779929 ps
CPU time	4424.17 seconds
Started	Jun 04 02:32:05 PM PDT 24
Finished	Jun 04 03:45:50 PM PDT 24
Peak memory	562448 kb
Host	smart-7c878fae-4dda-4531-a6fc-f3284793f0c6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2569922893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.2569922893 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/34.kmac_alert_test.595328508
Short name	T653
Test name
Test status
Simulation time	117442175 ps
CPU time	0.9 seconds
Started	Jun 04 02:32:42 PM PDT 24
Finished	Jun 04 02:32:43 PM PDT 24
Peak memory	218952 kb
Host	smart-f75550ad-323c-4707-adc3-45a5e21becee
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595328508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.595328508 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_alert_test/latest

Test location	/workspace/coverage/default/34.kmac_app.3178029830
Short name	T875
Test name
Test status
Simulation time	2369476714 ps
CPU time	13.84 seconds
Started	Jun 04 02:32:26 PM PDT 24
Finished	Jun 04 02:32:40 PM PDT 24
Peak memory	227508 kb
Host	smart-37ec6893-8c64-4ca4-9461-cf47f6f466cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3178029830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.3178029830 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_app/latest

Test location	/workspace/coverage/default/34.kmac_burst_write.709673294
Short name	T891
Test name
Test status
Simulation time	21861588582 ps
CPU time	630.69 seconds
Started	Jun 04 02:32:21 PM PDT 24
Finished	Jun 04 02:42:52 PM PDT 24
Peak memory	232964 kb
Host	smart-2554cb29-d989-40db-bece-2af790079fbc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=709673294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.709673294 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_burst_write/latest

Test location	/workspace/coverage/default/34.kmac_entropy_refresh.1313060546
Short name	T908
Test name
Test status
Simulation time	12099245220 ps
CPU time	310.51 seconds
Started	Jun 04 02:32:27 PM PDT 24
Finished	Jun 04 02:37:39 PM PDT 24
Peak memory	250496 kb
Host	smart-740907f1-4729-44a5-95ac-894d65afda0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1313060546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.1313060546 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/34.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/34.kmac_error.1769915279
Short name	T894
Test name
Test status
Simulation time	9517217944 ps
CPU time	54.09 seconds
Started	Jun 04 02:32:29 PM PDT 24
Finished	Jun 04 02:33:23 PM PDT 24
Peak memory	237820 kb
Host	smart-ff65a28f-1059-4d7a-a3d4-99079818273a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1769915279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.1769915279 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_error/latest

Test location	/workspace/coverage/default/34.kmac_key_error.3538807192
Short name	T718
Test name
Test status
Simulation time	346548607 ps
CPU time	2.95 seconds
Started	Jun 04 02:32:27 PM PDT 24
Finished	Jun 04 02:32:31 PM PDT 24
Peak memory	223236 kb
Host	smart-35bacee4-ab51-4cd5-bd1d-1a2cc76207c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3538807192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.3538807192 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_key_error/latest

Test location	/workspace/coverage/default/34.kmac_lc_escalation.1568306315
Short name	T402
Test name
Test status
Simulation time	45186762 ps
CPU time	1.35 seconds
Started	Jun 04 02:32:33 PM PDT 24
Finished	Jun 04 02:32:35 PM PDT 24
Peak memory	227328 kb
Host	smart-381105a4-f2d2-4557-b6e6-f235f0f0bfe1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1568306315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1568306315 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/34.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/34.kmac_long_msg_and_output.639323827
Short name	T383
Test name
Test status
Simulation time	8276797247 ps
CPU time	305.6 seconds
Started	Jun 04 02:32:20 PM PDT 24
Finished	Jun 04 02:37:26 PM PDT 24
Peak memory	246224 kb
Host	smart-457f7584-abe0-4e0b-8392-550f47610e5c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639323827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_an d_output.639323827 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/34.kmac_sideload.3475976181
Short name	T211
Test name
Test status
Simulation time	5847239504 ps
CPU time	176.29 seconds
Started	Jun 04 02:32:19 PM PDT 24
Finished	Jun 04 02:35:16 PM PDT 24
Peak memory	239644 kb
Host	smart-e9a79ff1-63e2-4e46-9133-60dd6fe3a99b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475976181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.3475976181 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_sideload/latest

Test location	/workspace/coverage/default/34.kmac_smoke.2435318874
Short name	T1054
Test name
Test status
Simulation time	3460805140 ps
CPU time	61.84 seconds
Started	Jun 04 02:32:13 PM PDT 24
Finished	Jun 04 02:33:15 PM PDT 24
Peak memory	223128 kb
Host	smart-a2027d10-5582-42ae-9d72-1fc4553c0aaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2435318874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.2435318874 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_smoke/latest

Test location	/workspace/coverage/default/34.kmac_stress_all.595829657
Short name	T481
Test name
Test status
Simulation time	19100595937 ps
CPU time	623.19 seconds
Started	Jun 04 02:32:33 PM PDT 24
Finished	Jun 04 02:42:57 PM PDT 24
Peak memory	309504 kb
Host	smart-bee76c6a-5a6c-4846-ab5d-c21571c1ab9a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=595829657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.595829657 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_stress_all/latest

Test location	/workspace/coverage/default/34.kmac_stress_all_with_rand_reset.2791913052
Short name	T80
Test name
Test status
Simulation time	275218340737 ps
CPU time	665.43 seconds
Started	Jun 04 02:32:34 PM PDT 24
Finished	Jun 04 02:43:40 PM PDT 24
Peak memory	260320 kb
Host	smart-64992bf7-3c7e-4103-9bcc-d2264c430bc8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2791913052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all_with_rand_reset.2791913052 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_kmac.1396330130
Short name	T449
Test name
Test status
Simulation time	462699256 ps
CPU time	5.51 seconds
Started	Jun 04 02:32:27 PM PDT 24
Finished	Jun 04 02:32:34 PM PDT 24
Peak memory	219376 kb
Host	smart-b0473831-3b1f-4079-a7a3-a4a8fe425f06
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396330130 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.kmac_test_vectors_kmac.1396330130 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_kmac_xof.930948913
Short name	T216
Test name
Test status
Simulation time	107773936 ps
CPU time	5.3 seconds
Started	Jun 04 02:32:27 PM PDT 24
Finished	Jun 04 02:32:33 PM PDT 24
Peak memory	219248 kb
Host	smart-f63a0f4c-7776-437d-aeb2-3b7000c04788
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930948913 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 34.kmac_test_vectors_kmac_xof.930948913 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_224.434776182
Short name	T941
Test name
Test status
Simulation time	105493527111 ps
CPU time	1811.96 seconds
Started	Jun 04 02:32:21 PM PDT 24
Finished	Jun 04 03:02:33 PM PDT 24
Peak memory	393428 kb
Host	smart-c815a92f-fd29-4ce4-b21f-3eac28a591ad
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=434776182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.434776182 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_256.3961644802
Short name	T262
Test name
Test status
Simulation time	20336555199 ps
CPU time	1857.41 seconds
Started	Jun 04 02:32:21 PM PDT 24
Finished	Jun 04 03:03:19 PM PDT 24
Peak memory	381712 kb
Host	smart-02fec4cf-46e4-427c-9fc5-5f2cd5966467
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3961644802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.3961644802 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_384.1181374283
Short name	T422
Test name
Test status
Simulation time	322282774907 ps
CPU time	1664.7 seconds
Started	Jun 04 02:32:20 PM PDT 24
Finished	Jun 04 03:00:05 PM PDT 24
Peak memory	339644 kb
Host	smart-63d180ac-b6a6-4d80-9c54-ca47a9ef8f83
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1181374283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.1181374283 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_512.311009499
Short name	T679
Test name
Test status
Simulation time	80863137749 ps
CPU time	1275.23 seconds
Started	Jun 04 02:32:27 PM PDT 24
Finished	Jun 04 02:53:43 PM PDT 24
Peak memory	297664 kb
Host	smart-c36fe064-d0a6-40e7-978e-e3526714686d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=311009499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.311009499 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_shake_128.2479524747
Short name	T234
Test name
Test status
Simulation time	921651001180 ps
CPU time	6040.6 seconds
Started	Jun 04 02:32:28 PM PDT 24
Finished	Jun 04 04:13:10 PM PDT 24
Peak memory	646556 kb
Host	smart-5902c6a7-8625-4c5b-941f-e3cb8418f614
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2479524747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.2479524747 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_shake_256.1248516159
Short name	T612
Test name
Test status
Simulation time	211932189282 ps
CPU time	4819.43 seconds
Started	Jun 04 02:32:27 PM PDT 24
Finished	Jun 04 03:52:48 PM PDT 24
Peak memory	566668 kb
Host	smart-4e6d08d4-e172-475f-ae9c-cb0710fc75e1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1248516159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.1248516159 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/35.kmac_alert_test.904620320
Short name	T290
Test name
Test status
Simulation time	53579842 ps
CPU time	0.93 seconds
Started	Jun 04 02:33:02 PM PDT 24
Finished	Jun 04 02:33:04 PM PDT 24
Peak memory	218952 kb
Host	smart-fbac1fa8-289b-4327-b69b-1df7d6f9c1b6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904620320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.904620320 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_alert_test/latest

Test location	/workspace/coverage/default/35.kmac_app.3584390545
Short name	T780
Test name
Test status
Simulation time	51765700997 ps
CPU time	294.43 seconds
Started	Jun 04 02:32:55 PM PDT 24
Finished	Jun 04 02:37:50 PM PDT 24
Peak memory	249192 kb
Host	smart-bf755190-f856-43d0-8ec0-486ddd8f950f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584390545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.3584390545 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_app/latest

Test location	/workspace/coverage/default/35.kmac_burst_write.2321855320
Short name	T416
Test name
Test status
Simulation time	44593216129 ps
CPU time	1008.19 seconds
Started	Jun 04 02:32:48 PM PDT 24
Finished	Jun 04 02:49:37 PM PDT 24
Peak memory	243852 kb
Host	smart-aeaf0f89-d2d6-4678-aa14-d69c84e355c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2321855320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.2321855320 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_burst_write/latest

Test location	/workspace/coverage/default/35.kmac_entropy_refresh.1506606686
Short name	T825
Test name
Test status
Simulation time	8358509234 ps
CPU time	100.07 seconds
Started	Jun 04 02:32:54 PM PDT 24
Finished	Jun 04 02:34:34 PM PDT 24
Peak memory	234228 kb
Host	smart-a66cef35-3946-404c-8940-173026511cae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1506606686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.1506606686 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/35.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/35.kmac_error.568312265
Short name	T834
Test name
Test status
Simulation time	68186240738 ps
CPU time	467.74 seconds
Started	Jun 04 02:32:55 PM PDT 24
Finished	Jun 04 02:40:43 PM PDT 24
Peak memory	268544 kb
Host	smart-37e88d02-90b1-4b73-a009-2629abb882f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=568312265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.568312265 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_error/latest

Test location	/workspace/coverage/default/35.kmac_key_error.2647751594
Short name	T257
Test name
Test status
Simulation time	911080438 ps
CPU time	7.09 seconds
Started	Jun 04 02:33:03 PM PDT 24
Finished	Jun 04 02:33:10 PM PDT 24
Peak memory	223888 kb
Host	smart-a86a8c7a-cc48-4f7e-8c30-bc7b225027b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2647751594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2647751594 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_key_error/latest

Test location	/workspace/coverage/default/35.kmac_lc_escalation.2459555086
Short name	T27
Test name
Test status
Simulation time	178543193 ps
CPU time	1.44 seconds
Started	Jun 04 02:33:02 PM PDT 24
Finished	Jun 04 02:33:04 PM PDT 24
Peak memory	227224 kb
Host	smart-7801bba9-1fde-49e0-8f1a-9597bce3f368
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2459555086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.2459555086 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/35.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/35.kmac_long_msg_and_output.2100055613
Short name	T683
Test name
Test status
Simulation time	38483578674 ps
CPU time	285.67 seconds
Started	Jun 04 02:32:40 PM PDT 24
Finished	Jun 04 02:37:26 PM PDT 24
Peak memory	246156 kb
Host	smart-f21e87df-365f-4634-ae89-5c3e8ad5135e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100055613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a nd_output.2100055613 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/35.kmac_sideload.2820628963
Short name	T493
Test name
Test status
Simulation time	83462356487 ps
CPU time	132.02 seconds
Started	Jun 04 02:32:46 PM PDT 24
Finished	Jun 04 02:34:59 PM PDT 24
Peak memory	234800 kb
Host	smart-471c702e-e0e0-4a77-a61e-35ad8aa0e8c4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820628963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.2820628963 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_sideload/latest

Test location	/workspace/coverage/default/35.kmac_smoke.802154768
Short name	T511
Test name
Test status
Simulation time	872815284 ps
CPU time	6.04 seconds
Started	Jun 04 02:32:41 PM PDT 24
Finished	Jun 04 02:32:48 PM PDT 24
Peak memory	226676 kb
Host	smart-fd32f528-18ca-499b-8ff8-bfd338181719
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=802154768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.802154768 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_smoke/latest

Test location	/workspace/coverage/default/35.kmac_stress_all.3777595016
Short name	T981
Test name
Test status
Simulation time	219203398803 ps
CPU time	1423.08 seconds
Started	Jun 04 02:33:02 PM PDT 24
Finished	Jun 04 02:56:46 PM PDT 24
Peak memory	322896 kb
Host	smart-56fcd7c5-9834-43dc-939e-5a325e429914
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3777595016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3777595016 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_stress_all/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_kmac.3207532319
Short name	T401
Test name
Test status
Simulation time	290991947 ps
CPU time	5.99 seconds
Started	Jun 04 02:32:55 PM PDT 24
Finished	Jun 04 02:33:02 PM PDT 24
Peak memory	219264 kb
Host	smart-b21c3720-f847-43d6-bd6c-257d52acd2ac
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207532319 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.kmac_test_vectors_kmac.3207532319 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_kmac_xof.2239573085
Short name	T202
Test name
Test status
Simulation time	449056082 ps
CPU time	6.43 seconds
Started	Jun 04 02:32:55 PM PDT 24
Finished	Jun 04 02:33:02 PM PDT 24
Peak memory	219284 kb
Host	smart-cc0ab6ff-46f4-4da4-bdc9-e241fc498f86
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239573085 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_kmac_xof.2239573085 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_224.1099392222
Short name	T575
Test name
Test status
Simulation time	80036782188 ps
CPU time	1877.31 seconds
Started	Jun 04 02:32:47 PM PDT 24
Finished	Jun 04 03:04:05 PM PDT 24
Peak memory	391276 kb
Host	smart-0e87d59e-5c6a-4d89-9ab4-66d89b732c60
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1099392222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.1099392222 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_256.2748527098
Short name	T263
Test name
Test status
Simulation time	65384536647 ps
CPU time	2073.35 seconds
Started	Jun 04 02:32:54 PM PDT 24
Finished	Jun 04 03:07:28 PM PDT 24
Peak memory	392200 kb
Host	smart-65bba614-e5d3-4172-b75b-71e1a79c19bd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2748527098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.2748527098 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_384.2859392954
Short name	T584
Test name
Test status
Simulation time	31183998446 ps
CPU time	1540.77 seconds
Started	Jun 04 02:32:53 PM PDT 24
Finished	Jun 04 02:58:34 PM PDT 24
Peak memory	343672 kb
Host	smart-a4dd48e8-9b46-406d-8ad3-21358646e93c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2859392954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.2859392954 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_512.2623827577
Short name	T568
Test name
Test status
Simulation time	50353549947 ps
CPU time	1357.12 seconds
Started	Jun 04 02:32:55 PM PDT 24
Finished	Jun 04 02:55:33 PM PDT 24
Peak memory	305340 kb
Host	smart-be592444-4ea2-495a-8dfe-5c1f979d64f7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2623827577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.2623827577 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_shake_128.2912823860
Short name	T978
Test name
Test status
Simulation time	241699937698 ps
CPU time	4666.14 seconds
Started	Jun 04 02:32:55 PM PDT 24
Finished	Jun 04 03:50:43 PM PDT 24
Peak memory	663840 kb
Host	smart-979407f4-18ec-4f2b-88d9-91f34b1a00dd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2912823860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.2912823860 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_shake_256.2775301630
Short name	T1032
Test name
Test status
Simulation time	161338834980 ps
CPU time	5255.84 seconds
Started	Jun 04 02:32:54 PM PDT 24
Finished	Jun 04 04:00:31 PM PDT 24
Peak memory	572080 kb
Host	smart-f49d78c7-d808-4b38-949e-1416ac1c79a3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2775301630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.2775301630 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/36.kmac_alert_test.807611753
Short name	T580
Test name
Test status
Simulation time	40314566 ps
CPU time	0.81 seconds
Started	Jun 04 02:33:23 PM PDT 24
Finished	Jun 04 02:33:24 PM PDT 24
Peak memory	218944 kb
Host	smart-dfd87ce9-2676-4756-862e-3bd5a37283c1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807611753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.807611753 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_alert_test/latest

Test location	/workspace/coverage/default/36.kmac_app.3950071253
Short name	T1058
Test name
Test status
Simulation time	55512817037 ps
CPU time	361.69 seconds
Started	Jun 04 02:33:16 PM PDT 24
Finished	Jun 04 02:39:19 PM PDT 24
Peak memory	250776 kb
Host	smart-ae0709a1-0ca2-41ac-9e2c-7a86ccae4e71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3950071253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3950071253 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_app/latest

Test location	/workspace/coverage/default/36.kmac_burst_write.3845848286
Short name	T109
Test name
Test status
Simulation time	131756931142 ps
CPU time	1723.29 seconds
Started	Jun 04 02:33:10 PM PDT 24
Finished	Jun 04 03:01:54 PM PDT 24
Peak memory	240244 kb
Host	smart-cf1f0910-3a1d-445c-bbeb-678358c30fa9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3845848286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.3845848286 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_burst_write/latest

Test location	/workspace/coverage/default/36.kmac_entropy_refresh.4275145759
Short name	T315
Test name
Test status
Simulation time	26148037267 ps
CPU time	117.06 seconds
Started	Jun 04 02:33:17 PM PDT 24
Finished	Jun 04 02:35:15 PM PDT 24
Peak memory	235748 kb
Host	smart-24563220-a356-41b4-ac1c-6d9fb65a5fbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4275145759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.4275145759 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/36.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/36.kmac_error.2224633764
Short name	T634
Test name
Test status
Simulation time	4577111217 ps
CPU time	384.13 seconds
Started	Jun 04 02:33:15 PM PDT 24
Finished	Jun 04 02:39:40 PM PDT 24
Peak memory	268532 kb
Host	smart-4c63f733-308a-4c17-ac14-3585bf95b231
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2224633764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.2224633764 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_error/latest

Test location	/workspace/coverage/default/36.kmac_key_error.2987550318
Short name	T433
Test name
Test status
Simulation time	3213255134 ps
CPU time	8.93 seconds
Started	Jun 04 02:33:15 PM PDT 24
Finished	Jun 04 02:33:25 PM PDT 24
Peak memory	225732 kb
Host	smart-92a524e7-60a1-4477-b473-e322a6ddf2d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2987550318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.2987550318 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_key_error/latest

Test location	/workspace/coverage/default/36.kmac_lc_escalation.211576885
Short name	T26
Test name
Test status
Simulation time	52406798 ps
CPU time	1.45 seconds
Started	Jun 04 02:33:23 PM PDT 24
Finished	Jun 04 02:33:25 PM PDT 24
Peak memory	227384 kb
Host	smart-9a987349-612c-4f52-a5a2-4d46055e6812
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=211576885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.211576885 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/36.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/36.kmac_long_msg_and_output.539042078
Short name	T903
Test name
Test status
Simulation time	67918968601 ps
CPU time	2446.08 seconds
Started	Jun 04 02:33:08 PM PDT 24
Finished	Jun 04 03:13:55 PM PDT 24
Peak memory	410488 kb
Host	smart-e7a33740-3c07-41b1-9aed-0a6a548d64cd
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539042078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_an d_output.539042078 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/36.kmac_sideload.2327355342
Short name	T391
Test name
Test status
Simulation time	23415851359 ps
CPU time	388.38 seconds
Started	Jun 04 02:33:09 PM PDT 24
Finished	Jun 04 02:39:38 PM PDT 24
Peak memory	254404 kb
Host	smart-8eb7b7c6-d6ed-4655-8c7f-3d655b85be08
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327355342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.2327355342 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_sideload/latest

Test location	/workspace/coverage/default/36.kmac_smoke.1171937829
Short name	T559
Test name
Test status
Simulation time	7761998270 ps
CPU time	46.23 seconds
Started	Jun 04 02:33:02 PM PDT 24
Finished	Jun 04 02:33:49 PM PDT 24
Peak memory	223616 kb
Host	smart-5f244463-398f-4ac3-b4c3-7f313d3d2631
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1171937829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.1171937829 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_smoke/latest

Test location	/workspace/coverage/default/36.kmac_stress_all.1635225768
Short name	T1068
Test name
Test status
Simulation time	96536495837 ps
CPU time	614.57 seconds
Started	Jun 04 02:33:23 PM PDT 24
Finished	Jun 04 02:43:38 PM PDT 24
Peak memory	306612 kb
Host	smart-5f1df6da-e3a1-44df-94e5-b82fafcc06ad
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1635225768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1635225768 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_stress_all/latest

Test location	/workspace/coverage/default/36.kmac_stress_all_with_rand_reset.2929775137
Short name	T60
Test name
Test status
Simulation time	311537920481 ps
CPU time	2611.65 seconds
Started	Jun 04 02:33:22 PM PDT 24
Finished	Jun 04 03:16:55 PM PDT 24
Peak memory	378912 kb
Host	smart-49517684-9a3b-4fc4-90ed-24f2fe2de09e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2929775137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all_with_rand_reset.2929775137 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_kmac.4098514792
Short name	T842
Test name
Test status
Simulation time	270763520 ps
CPU time	6.09 seconds
Started	Jun 04 02:33:17 PM PDT 24
Finished	Jun 04 02:33:24 PM PDT 24
Peak memory	219276 kb
Host	smart-19caff05-8927-4732-b4fe-ea2875a1c892
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098514792 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.kmac_test_vectors_kmac.4098514792 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_kmac_xof.4236009456
Short name	T434
Test name
Test status
Simulation time	359129768 ps
CPU time	5.99 seconds
Started	Jun 04 02:33:16 PM PDT 24
Finished	Jun 04 02:33:22 PM PDT 24
Peak memory	219264 kb
Host	smart-e67c4a4a-c2b3-4a90-adca-c872767465f8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236009456 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_kmac_xof.4236009456 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_224.2810165173
Short name	T307
Test name
Test status
Simulation time	97335596953 ps
CPU time	2379.51 seconds
Started	Jun 04 02:33:07 PM PDT 24
Finished	Jun 04 03:12:47 PM PDT 24
Peak memory	392420 kb
Host	smart-c090e85e-79ac-469c-9ffb-b69a97e893f6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2810165173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.2810165173 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_256.435914509
Short name	T540
Test name
Test status
Simulation time	190217653376 ps
CPU time	2169.41 seconds
Started	Jun 04 02:33:10 PM PDT 24
Finished	Jun 04 03:09:20 PM PDT 24
Peak memory	385908 kb
Host	smart-ef5d4a2d-16ae-4424-994f-d6b77e57d612
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=435914509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.435914509 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_384.3759107744
Short name	T462
Test name
Test status
Simulation time	496334513656 ps
CPU time	1833.36 seconds
Started	Jun 04 02:33:09 PM PDT 24
Finished	Jun 04 03:03:43 PM PDT 24
Peak memory	337284 kb
Host	smart-b47679a3-8ae4-4632-b4a9-26ae4fc5c5a3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3759107744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.3759107744 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_512.413671321
Short name	T768
Test name
Test status
Simulation time	182571819284 ps
CPU time	1238.66 seconds
Started	Jun 04 02:33:09 PM PDT 24
Finished	Jun 04 02:53:48 PM PDT 24
Peak memory	300784 kb
Host	smart-a07e4e7e-244b-4649-8215-48a0c2ca764a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=413671321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.413671321 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_shake_128.3488291572
Short name	T803
Test name
Test status
Simulation time	73180802792 ps
CPU time	5107.11 seconds
Started	Jun 04 02:33:08 PM PDT 24
Finished	Jun 04 03:58:16 PM PDT 24
Peak memory	623524 kb
Host	smart-b3c29a50-9cb8-4c7a-8c33-5025fe8c1ba5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3488291572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.3488291572 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_shake_256.3074031870
Short name	T39
Test name
Test status
Simulation time	54960491791 ps
CPU time	4851 seconds
Started	Jun 04 02:33:17 PM PDT 24
Finished	Jun 04 03:54:09 PM PDT 24
Peak memory	576408 kb
Host	smart-815ec7d6-adca-4a62-bc94-0ae8332354f2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3074031870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.3074031870 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/37.kmac_alert_test.750511596
Short name	T771
Test name
Test status
Simulation time	22551158 ps
CPU time	0.81 seconds
Started	Jun 04 02:33:51 PM PDT 24
Finished	Jun 04 02:33:53 PM PDT 24
Peak memory	218892 kb
Host	smart-38f9690e-b84f-4da0-99fd-2bcdfcd8e65b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750511596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.750511596 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_alert_test/latest

Test location	/workspace/coverage/default/37.kmac_app.165756328
Short name	T166
Test name
Test status
Simulation time	46725021927 ps
CPU time	274.94 seconds
Started	Jun 04 02:33:43 PM PDT 24
Finished	Jun 04 02:38:19 PM PDT 24
Peak memory	247300 kb
Host	smart-1290847b-6316-445c-81c3-d0edae55f5e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165756328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.165756328 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_app/latest

Test location	/workspace/coverage/default/37.kmac_burst_write.1543029676
Short name	T703
Test name
Test status
Simulation time	31753829928 ps
CPU time	1647.68 seconds
Started	Jun 04 02:33:39 PM PDT 24
Finished	Jun 04 03:01:08 PM PDT 24
Peak memory	240612 kb
Host	smart-a0a7b450-d806-4588-a9a0-3e715c1445fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1543029676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.1543029676 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_burst_write/latest

Test location	/workspace/coverage/default/37.kmac_entropy_refresh.3017690686
Short name	T769
Test name
Test status
Simulation time	11258190691 ps
CPU time	251.04 seconds
Started	Jun 04 02:33:44 PM PDT 24
Finished	Jun 04 02:37:55 PM PDT 24
Peak memory	244200 kb
Host	smart-7f169c50-a4a9-4aec-98f4-7aa5b5443407
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017690686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.3017690686 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/37.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/37.kmac_error.1292795060
Short name	T645
Test name
Test status
Simulation time	13646898803 ps
CPU time	396.57 seconds
Started	Jun 04 02:33:48 PM PDT 24
Finished	Jun 04 02:40:25 PM PDT 24
Peak memory	260220 kb
Host	smart-c0b29509-df74-4a7e-af8d-aae8302bc0bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1292795060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1292795060 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_error/latest

Test location	/workspace/coverage/default/37.kmac_lc_escalation.297316352
Short name	T898
Test name
Test status
Simulation time	102549161 ps
CPU time	1.35 seconds
Started	Jun 04 02:33:51 PM PDT 24
Finished	Jun 04 02:33:53 PM PDT 24
Peak memory	227260 kb
Host	smart-7deeae2f-3875-459c-8f77-637fac8ae8db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=297316352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.297316352 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/37.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/37.kmac_long_msg_and_output.470788771
Short name	T336
Test name
Test status
Simulation time	47393195763 ps
CPU time	485.14 seconds
Started	Jun 04 02:33:33 PM PDT 24
Finished	Jun 04 02:41:38 PM PDT 24
Peak memory	260268 kb
Host	smart-f48b6b8f-1501-48c2-b17a-6a2c2860583e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470788771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_an d_output.470788771 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/37.kmac_sideload.1970145926
Short name	T896
Test name
Test status
Simulation time	8606311413 ps
CPU time	184.9 seconds
Started	Jun 04 02:33:37 PM PDT 24
Finished	Jun 04 02:36:43 PM PDT 24
Peak memory	243868 kb
Host	smart-e168fd64-c1e9-4e56-ac73-b1af51987f41
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970145926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.1970145926 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_sideload/latest

Test location	/workspace/coverage/default/37.kmac_smoke.1557961636
Short name	T624
Test name
Test status
Simulation time	1304503265 ps
CPU time	52.06 seconds
Started	Jun 04 02:33:24 PM PDT 24
Finished	Jun 04 02:34:17 PM PDT 24
Peak memory	223784 kb
Host	smart-98f7ee64-48e5-4327-9cb9-546508b4c9ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1557961636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.1557961636 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_smoke/latest

Test location	/workspace/coverage/default/37.kmac_stress_all.903015212
Short name	T1053
Test name
Test status
Simulation time	72887347010 ps
CPU time	1963.38 seconds
Started	Jun 04 02:33:50 PM PDT 24
Finished	Jun 04 03:06:34 PM PDT 24
Peak memory	384056 kb
Host	smart-ba8365e0-a457-44df-b53a-c17e3c29c69f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=903015212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.903015212 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_stress_all/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_kmac.520629135
Short name	T340
Test name
Test status
Simulation time	425533983 ps
CPU time	7.14 seconds
Started	Jun 04 02:33:44 PM PDT 24
Finished	Jun 04 02:33:51 PM PDT 24
Peak memory	219180 kb
Host	smart-f8d0d08a-af07-44be-bb37-5a94aabf8f73
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520629135 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 37.kmac_test_vectors_kmac.520629135 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_kmac_xof.521409367
Short name	T309
Test name
Test status
Simulation time	132353706 ps
CPU time	5.31 seconds
Started	Jun 04 02:33:47 PM PDT 24
Finished	Jun 04 02:33:53 PM PDT 24
Peak memory	219304 kb
Host	smart-b9cb9f80-79ba-4f8f-a4f6-51bf290a0d24
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521409367 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 37.kmac_test_vectors_kmac_xof.521409367 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_224.2640299593
Short name	T1040
Test name
Test status
Simulation time	128171190008 ps
CPU time	2027.97 seconds
Started	Jun 04 02:33:41 PM PDT 24
Finished	Jun 04 03:07:29 PM PDT 24
Peak memory	402712 kb
Host	smart-1e46dcc6-030b-45eb-a8ea-be0ec3ebe1d5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2640299593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.2640299593 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_256.2848242223
Short name	T188
Test name
Test status
Simulation time	101301728245 ps
CPU time	1938.38 seconds
Started	Jun 04 02:33:47 PM PDT 24
Finished	Jun 04 03:06:06 PM PDT 24
Peak memory	384964 kb
Host	smart-4eeb28f7-47d3-42b6-9e2f-445ecf8e815f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2848242223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.2848242223 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_384.1711566288
Short name	T1005
Test name
Test status
Simulation time	64926505000 ps
CPU time	1601.48 seconds
Started	Jun 04 02:33:44 PM PDT 24
Finished	Jun 04 03:00:26 PM PDT 24
Peak memory	342496 kb
Host	smart-ac65ceb1-2d58-45a6-acfb-489e06a26d85
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1711566288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.1711566288 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_512.2229678372
Short name	T476
Test name
Test status
Simulation time	49732592238 ps
CPU time	1050.55 seconds
Started	Jun 04 02:33:44 PM PDT 24
Finished	Jun 04 02:51:15 PM PDT 24
Peak memory	301044 kb
Host	smart-8dcd6a10-de73-4b68-b48f-dde078716efd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2229678372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.2229678372 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_shake_128.2535234588
Short name	T1055
Test name
Test status
Simulation time	62657882944 ps
CPU time	5463.75 seconds
Started	Jun 04 02:33:43 PM PDT 24
Finished	Jun 04 04:04:49 PM PDT 24
Peak memory	662452 kb
Host	smart-622da997-8a9a-42f5-b91f-dbca0312974a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2535234588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.2535234588 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_shake_256.2265408767
Short name	T370
Test name
Test status
Simulation time	3044011863635 ps
CPU time	6040.71 seconds
Started	Jun 04 02:33:44 PM PDT 24
Finished	Jun 04 04:14:26 PM PDT 24
Peak memory	580360 kb
Host	smart-9cce05f3-4d0a-45ac-96ed-851960683d37
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2265408767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.2265408767 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/38.kmac_alert_test.50664765
Short name	T116
Test name
Test status
Simulation time	47082988 ps
CPU time	0.84 seconds
Started	Jun 04 02:34:19 PM PDT 24
Finished	Jun 04 02:34:20 PM PDT 24
Peak memory	218948 kb
Host	smart-9174529f-b36d-4384-a9fd-664e4240bdcf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50664765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.50664765 +enable_mas king=1 +sw_key_masked=0
Directory	/workspace/38.kmac_alert_test/latest

Test location	/workspace/coverage/default/38.kmac_app.1229357516
Short name	T435
Test name
Test status
Simulation time	6489510822 ps
CPU time	302.66 seconds
Started	Jun 04 02:34:11 PM PDT 24
Finished	Jun 04 02:39:15 PM PDT 24
Peak memory	248300 kb
Host	smart-bea80896-8e99-41fa-83fb-397edaf4de36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1229357516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1229357516 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_app/latest

Test location	/workspace/coverage/default/38.kmac_burst_write.835022446
Short name	T893
Test name
Test status
Simulation time	5674269223 ps
CPU time	261.04 seconds
Started	Jun 04 02:34:00 PM PDT 24
Finished	Jun 04 02:38:22 PM PDT 24
Peak memory	238528 kb
Host	smart-3c99be02-bc4c-4161-a91c-796302ffc38f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=835022446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.835022446 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_burst_write/latest

Test location	/workspace/coverage/default/38.kmac_entropy_refresh.365344362
Short name	T787
Test name
Test status
Simulation time	36297406505 ps
CPU time	319 seconds
Started	Jun 04 02:34:11 PM PDT 24
Finished	Jun 04 02:39:31 PM PDT 24
Peak memory	247372 kb
Host	smart-13fa2f5d-746b-4318-ac2d-698728475580
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=365344362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.365344362 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/38.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/38.kmac_error.3057232395
Short name	T157
Test name
Test status
Simulation time	11540339647 ps
CPU time	292.41 seconds
Started	Jun 04 02:34:11 PM PDT 24
Finished	Jun 04 02:39:04 PM PDT 24
Peak memory	260248 kb
Host	smart-e4b5a342-d6e4-4f65-a638-ef54f974e0b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057232395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.3057232395 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_error/latest

Test location	/workspace/coverage/default/38.kmac_key_error.4222873179
Short name	T121
Test name
Test status
Simulation time	2735266134 ps
CPU time	12.24 seconds
Started	Jun 04 02:34:11 PM PDT 24
Finished	Jun 04 02:34:23 PM PDT 24
Peak memory	226808 kb
Host	smart-0fb8f1f9-f67f-4206-a332-e7bd669f224d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4222873179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.4222873179 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_key_error/latest

Test location	/workspace/coverage/default/38.kmac_lc_escalation.3622779804
Short name	T618
Test name
Test status
Simulation time	46250073 ps
CPU time	1.38 seconds
Started	Jun 04 02:34:25 PM PDT 24
Finished	Jun 04 02:34:27 PM PDT 24
Peak memory	226796 kb
Host	smart-e940de2c-53f6-4bac-a8dc-ef52dc0326f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3622779804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3622779804 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/38.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/38.kmac_long_msg_and_output.3949649032
Short name	T686
Test name
Test status
Simulation time	1892818215 ps
CPU time	51.56 seconds
Started	Jun 04 02:33:58 PM PDT 24
Finished	Jun 04 02:34:50 PM PDT 24
Peak memory	222712 kb
Host	smart-05402ee5-1c63-4317-9c00-b0eefd42a3dc
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949649032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a nd_output.3949649032 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/38.kmac_smoke.2914293576
Short name	T900
Test name
Test status
Simulation time	3464767378 ps
CPU time	41.56 seconds
Started	Jun 04 02:33:58 PM PDT 24
Finished	Jun 04 02:34:40 PM PDT 24
Peak memory	227456 kb
Host	smart-0b5cf0e1-8e20-42ea-8ff8-97f8ce2cda27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2914293576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.2914293576 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_smoke/latest

Test location	/workspace/coverage/default/38.kmac_stress_all.672698821
Short name	T676
Test name
Test status
Simulation time	259758256458 ps
CPU time	2571.51 seconds
Started	Jun 04 02:34:24 PM PDT 24
Finished	Jun 04 03:17:17 PM PDT 24
Peak memory	388432 kb
Host	smart-6cac3067-5af3-4eb9-b6c1-e93a17c1a3ce
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=672698821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.672698821 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_stress_all/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_kmac.2239546500
Short name	T946
Test name
Test status
Simulation time	214456287 ps
CPU time	5.67 seconds
Started	Jun 04 02:34:09 PM PDT 24
Finished	Jun 04 02:34:16 PM PDT 24
Peak memory	219332 kb
Host	smart-06043498-3720-4d47-9164-d1937cb71d43
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239546500 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.kmac_test_vectors_kmac.2239546500 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_kmac_xof.2429484506
Short name	T430
Test name
Test status
Simulation time	498686288 ps
CPU time	6.32 seconds
Started	Jun 04 02:34:10 PM PDT 24
Finished	Jun 04 02:34:17 PM PDT 24
Peak memory	219268 kb
Host	smart-ab20b440-6e05-4138-99ad-d4fd789116dd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429484506 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_kmac_xof.2429484506 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_224.2204820265
Short name	T439
Test name
Test status
Simulation time	22046201358 ps
CPU time	2045 seconds
Started	Jun 04 02:34:12 PM PDT 24
Finished	Jun 04 03:08:17 PM PDT 24
Peak memory	395972 kb
Host	smart-7439a007-cb7f-428e-a0e7-265c3260d6a5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2204820265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.2204820265 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_256.419547556
Short name	T253
Test name
Test status
Simulation time	373789951095 ps
CPU time	2287.96 seconds
Started	Jun 04 02:34:17 PM PDT 24
Finished	Jun 04 03:12:26 PM PDT 24
Peak memory	379224 kb
Host	smart-f5b45df6-e4cb-4bde-ac61-be16b7a6ad29
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=419547556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.419547556 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_384.4148272038
Short name	T822
Test name
Test status
Simulation time	30786829336 ps
CPU time	1451.37 seconds
Started	Jun 04 02:34:13 PM PDT 24
Finished	Jun 04 02:58:25 PM PDT 24
Peak memory	334016 kb
Host	smart-ebb1f5a0-fcf6-49ec-b965-6670a48dca74
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4148272038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.4148272038 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_512.2540106853
Short name	T709
Test name
Test status
Simulation time	47297981287 ps
CPU time	1228.31 seconds
Started	Jun 04 02:34:11 PM PDT 24
Finished	Jun 04 02:54:40 PM PDT 24
Peak memory	298624 kb
Host	smart-60086087-4d96-4bbb-b514-dab17bbc49e8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2540106853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.2540106853 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_shake_128.3252558292
Short name	T772
Test name
Test status
Simulation time	238177536521 ps
CPU time	6131.69 seconds
Started	Jun 04 02:34:11 PM PDT 24
Finished	Jun 04 04:16:24 PM PDT 24
Peak memory	660180 kb
Host	smart-16b1f0df-1a6a-4b7d-a385-18f769c274d6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3252558292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.3252558292 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_shake_256.383610643
Short name	T899
Test name
Test status
Simulation time	765536307928 ps
CPU time	5224.81 seconds
Started	Jun 04 02:34:11 PM PDT 24
Finished	Jun 04 04:01:18 PM PDT 24
Peak memory	566408 kb
Host	smart-366e8f30-ddf0-486b-a619-1e17fb98c13b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=383610643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.383610643 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/39.kmac_alert_test.3254310007
Short name	T841
Test name
Test status
Simulation time	102280469 ps
CPU time	0.89 seconds
Started	Jun 04 02:34:40 PM PDT 24
Finished	Jun 04 02:34:42 PM PDT 24
Peak memory	218900 kb
Host	smart-d996190f-a9f5-4761-8e0f-874862ebf06d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254310007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3254310007 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_alert_test/latest

Test location	/workspace/coverage/default/39.kmac_app.2046630033
Short name	T720
Test name
Test status
Simulation time	5926463509 ps
CPU time	301.41 seconds
Started	Jun 04 02:34:35 PM PDT 24
Finished	Jun 04 02:39:37 PM PDT 24
Peak memory	250040 kb
Host	smart-b8de7228-2db9-424c-b3c3-fcf413fbc039
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2046630033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2046630033 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_app/latest

Test location	/workspace/coverage/default/39.kmac_burst_write.3442396215
Short name	T454
Test name
Test status
Simulation time	62354779776 ps
CPU time	703.62 seconds
Started	Jun 04 02:34:25 PM PDT 24
Finished	Jun 04 02:46:09 PM PDT 24
Peak memory	234296 kb
Host	smart-0c97236f-17f5-4d9c-9c77-e719d19fe2d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3442396215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.3442396215 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_burst_write/latest

Test location	/workspace/coverage/default/39.kmac_entropy_refresh.1407207547
Short name	T273
Test name
Test status
Simulation time	7478839923 ps
CPU time	202.23 seconds
Started	Jun 04 02:34:33 PM PDT 24
Finished	Jun 04 02:37:56 PM PDT 24
Peak memory	244892 kb
Host	smart-1d3c21ea-463d-45e2-8e6e-292f3f14f3dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1407207547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1407207547 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/39.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/39.kmac_error.49028013
Short name	T376
Test name
Test status
Simulation time	13102988170 ps
CPU time	430.15 seconds
Started	Jun 04 02:34:34 PM PDT 24
Finished	Jun 04 02:41:44 PM PDT 24
Peak memory	268416 kb
Host	smart-b64cf669-6ad8-4027-b579-e557f15fec6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=49028013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.49028013 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_error/latest

Test location	/workspace/coverage/default/39.kmac_key_error.3544220385
Short name	T746
Test name
Test status
Simulation time	3524729357 ps
CPU time	9.64 seconds
Started	Jun 04 02:34:34 PM PDT 24
Finished	Jun 04 02:34:45 PM PDT 24
Peak memory	225408 kb
Host	smart-b9bc749e-40be-493e-8730-c7db52308ac3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3544220385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.3544220385 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_key_error/latest

Test location	/workspace/coverage/default/39.kmac_lc_escalation.2820904068
Short name	T363
Test name
Test status
Simulation time	993542078 ps
CPU time	31.63 seconds
Started	Jun 04 02:34:35 PM PDT 24
Finished	Jun 04 02:35:07 PM PDT 24
Peak memory	235496 kb
Host	smart-be938478-ce7c-442a-8232-e83fe07a75e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2820904068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2820904068 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/39.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/39.kmac_long_msg_and_output.308479459
Short name	T470
Test name
Test status
Simulation time	36283785631 ps
CPU time	1046.2 seconds
Started	Jun 04 02:34:25 PM PDT 24
Finished	Jun 04 02:51:52 PM PDT 24
Peak memory	305472 kb
Host	smart-b59cf83a-2a03-4dab-b9a6-dd7d2bc3a95a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308479459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_an d_output.308479459 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/39.kmac_sideload.3865686063
Short name	T807
Test name
Test status
Simulation time	11170484078 ps
CPU time	143.07 seconds
Started	Jun 04 02:34:20 PM PDT 24
Finished	Jun 04 02:36:44 PM PDT 24
Peak memory	243264 kb
Host	smart-beff148f-77ab-4d3f-84aa-6f12597d1e02
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865686063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.3865686063 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_sideload/latest

Test location	/workspace/coverage/default/39.kmac_smoke.4293313464
Short name	T927
Test name
Test status
Simulation time	3873154289 ps
CPU time	73.09 seconds
Started	Jun 04 02:34:24 PM PDT 24
Finished	Jun 04 02:35:38 PM PDT 24
Peak memory	223056 kb
Host	smart-fb2c59ae-7760-4c19-8316-852edebdc575
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4293313464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.4293313464 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_smoke/latest

Test location	/workspace/coverage/default/39.kmac_stress_all.1646112569
Short name	T717
Test name
Test status
Simulation time	18668289990 ps
CPU time	575.65 seconds
Started	Jun 04 02:34:35 PM PDT 24
Finished	Jun 04 02:44:11 PM PDT 24
Peak memory	270536 kb
Host	smart-390d049d-0a95-4caa-8d1b-c37dca824b72
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1646112569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.1646112569 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_stress_all/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_kmac.2282275785
Short name	T892
Test name
Test status
Simulation time	384568127 ps
CPU time	5.43 seconds
Started	Jun 04 02:34:34 PM PDT 24
Finished	Jun 04 02:34:40 PM PDT 24
Peak memory	219268 kb
Host	smart-3cb99591-fe5d-43c7-8c5d-bd7e5a1463c8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282275785 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 39.kmac_test_vectors_kmac.2282275785 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_kmac_xof.3531729694
Short name	T922
Test name
Test status
Simulation time	183013880 ps
CPU time	6.05 seconds
Started	Jun 04 02:34:35 PM PDT 24
Finished	Jun 04 02:34:41 PM PDT 24
Peak memory	219268 kb
Host	smart-515d9f84-c741-4a5f-b6cc-10ab98dac037
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531729694 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_kmac_xof.3531729694 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_224.1250552544
Short name	T67
Test name
Test status
Simulation time	182831324895 ps
CPU time	1784.12 seconds
Started	Jun 04 02:34:27 PM PDT 24
Finished	Jun 04 03:04:12 PM PDT 24
Peak memory	394524 kb
Host	smart-7e430633-bc07-4788-8eb7-1b3d235f2539
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1250552544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.1250552544 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_256.2671603472
Short name	T325
Test name
Test status
Simulation time	20043397495 ps
CPU time	1945.14 seconds
Started	Jun 04 02:34:26 PM PDT 24
Finished	Jun 04 03:06:52 PM PDT 24
Peak memory	392028 kb
Host	smart-507715e8-2b0e-46af-84bb-d8f7b3e610ea
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2671603472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.2671603472 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_384.4026895892
Short name	T479
Test name
Test status
Simulation time	75706313978 ps
CPU time	1664.59 seconds
Started	Jun 04 02:34:27 PM PDT 24
Finished	Jun 04 03:02:12 PM PDT 24
Peak memory	342800 kb
Host	smart-c42478d7-3063-475c-8d44-2e186322f291
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4026895892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.4026895892 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_512.1532683879
Short name	T1012
Test name
Test status
Simulation time	34899166039 ps
CPU time	1232.82 seconds
Started	Jun 04 02:34:28 PM PDT 24
Finished	Jun 04 02:55:02 PM PDT 24
Peak memory	307516 kb
Host	smart-6a72a417-012c-4af2-82a1-eaf9c3fd8615
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1532683879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.1532683879 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_shake_128.1128444072
Short name	T417
Test name
Test status
Simulation time	882319885961 ps
CPU time	5252.69 seconds
Started	Jun 04 02:34:27 PM PDT 24
Finished	Jun 04 04:02:01 PM PDT 24
Peak memory	668520 kb
Host	smart-962184c4-d73b-4e14-a27e-f326fd74fadf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1128444072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.1128444072 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_shake_256.3003425207
Short name	T152
Test name
Test status
Simulation time	243281273355 ps
CPU time	5573.3 seconds
Started	Jun 04 02:34:35 PM PDT 24
Finished	Jun 04 04:07:29 PM PDT 24
Peak memory	585472 kb
Host	smart-d11c14b4-7f15-42aa-96c3-aec60d6aab73
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3003425207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.3003425207 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/4.kmac_alert_test.3940025077
Short name	T648
Test name
Test status
Simulation time	88402513 ps
CPU time	0.78 seconds
Started	Jun 04 02:23:54 PM PDT 24
Finished	Jun 04 02:23:56 PM PDT 24
Peak memory	218964 kb
Host	smart-6ad50ad2-7c58-44d1-84b4-cfea8ae755a5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940025077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3940025077 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_alert_test/latest

Test location	/workspace/coverage/default/4.kmac_app.1228776847
Short name	T513
Test name
Test status
Simulation time	25095080981 ps
CPU time	375.46 seconds
Started	Jun 04 02:23:54 PM PDT 24
Finished	Jun 04 02:30:10 PM PDT 24
Peak memory	254200 kb
Host	smart-21e3752f-5096-4e47-bed2-7a6381327ef1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1228776847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.1228776847 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_app/latest

Test location	/workspace/coverage/default/4.kmac_app_with_partial_data.1273249970
Short name	T692
Test name
Test status
Simulation time	9785550606 ps
CPU time	190.16 seconds
Started	Jun 04 02:23:50 PM PDT 24
Finished	Jun 04 02:27:01 PM PDT 24
Peak memory	244780 kb
Host	smart-d142e02e-61f5-4d33-8540-46905ae1c468
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1273249970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.1273249970 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/4.kmac_burst_write.4065845688
Short name	T103
Test name
Test status
Simulation time	4733330257 ps
CPU time	544.69 seconds
Started	Jun 04 02:23:56 PM PDT 24
Finished	Jun 04 02:33:02 PM PDT 24
Peak memory	232512 kb
Host	smart-7e1a3016-54f3-4623-9ad5-331d4c405250
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4065845688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.4065845688 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_burst_write/latest

Test location	/workspace/coverage/default/4.kmac_edn_timeout_error.2303739631
Short name	T372
Test name
Test status
Simulation time	88727511 ps
CPU time	1.18 seconds
Started	Jun 04 02:23:54 PM PDT 24
Finished	Jun 04 02:23:56 PM PDT 24
Peak memory	224136 kb
Host	smart-c2ec1de5-8966-405d-8704-3b1acdf5b5fd
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2303739631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.2303739631 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_mode_error.552019988
Short name	T75
Test name
Test status
Simulation time	242271129 ps
CPU time	1.33 seconds
Started	Jun 04 02:23:57 PM PDT 24
Finished	Jun 04 02:23:59 PM PDT 24
Peak memory	222616 kb
Host	smart-4ea23266-73d8-412d-9831-5b256e9de304
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=552019988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.552019988 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_ready_error.640525638
Short name	T882
Test name
Test status
Simulation time	1596391882 ps
CPU time	10.62 seconds
Started	Jun 04 02:23:51 PM PDT 24
Finished	Jun 04 02:24:03 PM PDT 24
Peak memory	227288 kb
Host	smart-8c63ff25-53e7-4dd0-b554-4aab8a1ac58c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=640525638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.640525638 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspace/4.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_refresh.3421656914
Short name	T447
Test name
Test status
Simulation time	22814538397 ps
CPU time	215.46 seconds
Started	Jun 04 02:23:54 PM PDT 24
Finished	Jun 04 02:27:30 PM PDT 24
Peak memory	244060 kb
Host	smart-4b76fb0b-25bb-48b1-9045-15e893b11312
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3421656914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.3421656914 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/4.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/4.kmac_error.1643435868
Short name	T342
Test name
Test status
Simulation time	102780818307 ps
CPU time	292.65 seconds
Started	Jun 04 02:23:54 PM PDT 24
Finished	Jun 04 02:28:48 PM PDT 24
Peak memory	254908 kb
Host	smart-c0f1e1ea-b46e-4c30-b64a-8f186b9e7fdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1643435868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.1643435868 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_error/latest

Test location	/workspace/coverage/default/4.kmac_key_error.2235720785
Short name	T424
Test name
Test status
Simulation time	3721698048 ps
CPU time	5.36 seconds
Started	Jun 04 02:23:55 PM PDT 24
Finished	Jun 04 02:24:01 PM PDT 24
Peak memory	224380 kb
Host	smart-40f932ee-52f5-45bc-9552-264a7429055b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2235720785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2235720785 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_key_error/latest

Test location	/workspace/coverage/default/4.kmac_lc_escalation.517134787
Short name	T904
Test name
Test status
Simulation time	51534176 ps
CPU time	1.43 seconds
Started	Jun 04 02:23:59 PM PDT 24
Finished	Jun 04 02:24:01 PM PDT 24
Peak memory	227392 kb
Host	smart-69109ed2-0348-42d4-9577-a5c8962cfae2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=517134787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.517134787 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/4.kmac_long_msg_and_output.3408174116
Short name	T329
Test name
Test status
Simulation time	52936033078 ps
CPU time	1389.59 seconds
Started	Jun 04 02:23:44 PM PDT 24
Finished	Jun 04 02:46:54 PM PDT 24
Peak memory	338084 kb
Host	smart-9e6db7f2-c398-47c1-a853-c1df0c774a48
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408174116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an d_output.3408174116 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/4.kmac_mubi.2693396753
Short name	T52
Test name
Test status
Simulation time	7138290553 ps
CPU time	181.5 seconds
Started	Jun 04 02:23:51 PM PDT 24
Finished	Jun 04 02:26:53 PM PDT 24
Peak memory	242580 kb
Host	smart-3e7e0b3e-89b2-4f07-828b-4eacee6856a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2693396753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.2693396753 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_mubi/latest

Test location	/workspace/coverage/default/4.kmac_sideload.777901238
Short name	T220
Test name
Test status
Simulation time	7142212228 ps
CPU time	180.73 seconds
Started	Jun 04 02:23:42 PM PDT 24
Finished	Jun 04 02:26:43 PM PDT 24
Peak memory	238364 kb
Host	smart-d10899d9-b01a-4bb3-807a-2d7c5b59c55e
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777901238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.777901238 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_sideload/latest

Test location	/workspace/coverage/default/4.kmac_smoke.2060314500
Short name	T289
Test name
Test status
Simulation time	3806704480 ps
CPU time	36.61 seconds
Started	Jun 04 02:23:54 PM PDT 24
Finished	Jun 04 02:24:31 PM PDT 24
Peak memory	227352 kb
Host	smart-8f331e52-4f2e-49bc-b3d1-ca12f106b0d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2060314500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.2060314500 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_smoke/latest

Test location	/workspace/coverage/default/4.kmac_stress_all.85605263
Short name	T604
Test name
Test status
Simulation time	205501674319 ps
CPU time	924.79 seconds
Started	Jun 04 02:23:51 PM PDT 24
Finished	Jun 04 02:39:17 PM PDT 24
Peak memory	302984 kb
Host	smart-0a46248f-2062-40c7-aa39-59d374ff022a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=85605263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.85605263 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_stress_all/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_kmac.1278077985
Short name	T600
Test name
Test status
Simulation time	486556356 ps
CPU time	6.52 seconds
Started	Jun 04 02:23:54 PM PDT 24
Finished	Jun 04 02:24:01 PM PDT 24
Peak memory	219292 kb
Host	smart-3f25eaf5-8a67-4d1c-9398-bdabeb42d8c5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278077985 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.kmac_test_vectors_kmac.1278077985 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_kmac_xof.456395249
Short name	T785
Test name
Test status
Simulation time	934068283 ps
CPU time	5.94 seconds
Started	Jun 04 02:23:56 PM PDT 24
Finished	Jun 04 02:24:02 PM PDT 24
Peak memory	219312 kb
Host	smart-f8b59099-de04-4fb6-8710-9c4cd8757d25
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456395249 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.kmac_test_vectors_kmac_xof.456395249 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_224.527107371
Short name	T869
Test name
Test status
Simulation time	21129434615 ps
CPU time	2046.83 seconds
Started	Jun 04 02:23:51 PM PDT 24
Finished	Jun 04 02:57:59 PM PDT 24
Peak memory	398884 kb
Host	smart-d6387e92-c77a-4e45-ba15-3a81ac38a0ac
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=527107371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.527107371 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_256.2616958913
Short name	T247
Test name
Test status
Simulation time	282238349521 ps
CPU time	2066.18 seconds
Started	Jun 04 02:23:55 PM PDT 24
Finished	Jun 04 02:58:23 PM PDT 24
Peak memory	390384 kb
Host	smart-9525dd5c-ae52-46fc-84f2-11562a08613a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2616958913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.2616958913 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_384.3687964353
Short name	T468
Test name
Test status
Simulation time	16483206607 ps
CPU time	1575.53 seconds
Started	Jun 04 02:23:42 PM PDT 24
Finished	Jun 04 02:49:59 PM PDT 24
Peak memory	341872 kb
Host	smart-cf36b905-f26a-4e2f-93b6-83320ba9f03d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3687964353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.3687964353 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_512.2265648272
Short name	T863
Test name
Test status
Simulation time	703748000490 ps
CPU time	1246.99 seconds
Started	Jun 04 02:23:42 PM PDT 24
Finished	Jun 04 02:44:30 PM PDT 24
Peak memory	302452 kb
Host	smart-7445aaee-91cf-4a8e-8c26-e860208da6fa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2265648272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.2265648272 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_shake_128.1951850198
Short name	T111
Test name
Test status
Simulation time	1067986347480 ps
CPU time	6411.98 seconds
Started	Jun 04 02:23:43 PM PDT 24
Finished	Jun 04 04:10:36 PM PDT 24
Peak memory	646348 kb
Host	smart-08e6cb24-6893-4203-a1c5-5ca3f87065c7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1951850198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.1951850198 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_shake_256.336689341
Short name	T387
Test name
Test status
Simulation time	788891222501 ps
CPU time	5041.39 seconds
Started	Jun 04 02:23:56 PM PDT 24
Finished	Jun 04 03:47:59 PM PDT 24
Peak memory	565316 kb
Host	smart-f2a62679-89c9-4699-87a2-274fc3e2918f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=336689341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.336689341 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/40.kmac_alert_test.860621563
Short name	T690
Test name
Test status
Simulation time	17555554 ps
CPU time	0.86 seconds
Started	Jun 04 02:35:19 PM PDT 24
Finished	Jun 04 02:35:20 PM PDT 24
Peak memory	218948 kb
Host	smart-447551a4-0738-422d-897e-34945f588608
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860621563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.860621563 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_alert_test/latest

Test location	/workspace/coverage/default/40.kmac_app.1245455660
Short name	T911
Test name
Test status
Simulation time	22672094329 ps
CPU time	369.05 seconds
Started	Jun 04 02:34:57 PM PDT 24
Finished	Jun 04 02:41:06 PM PDT 24
Peak memory	250720 kb
Host	smart-dddd862b-954c-4236-824c-ed09fe1f403a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1245455660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.1245455660 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_app/latest

Test location	/workspace/coverage/default/40.kmac_burst_write.368172804
Short name	T646
Test name
Test status
Simulation time	26612753448 ps
CPU time	638.81 seconds
Started	Jun 04 02:34:48 PM PDT 24
Finished	Jun 04 02:45:27 PM PDT 24
Peak memory	235860 kb
Host	smart-fe6f5e44-8b66-4510-9480-42e421d8dc74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=368172804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.368172804 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_burst_write/latest

Test location	/workspace/coverage/default/40.kmac_entropy_refresh.693588046
Short name	T739
Test name
Test status
Simulation time	28997339256 ps
CPU time	341.88 seconds
Started	Jun 04 02:35:02 PM PDT 24
Finished	Jun 04 02:40:45 PM PDT 24
Peak memory	247264 kb
Host	smart-e9496548-b2b3-4622-9cce-e92244f572cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=693588046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.693588046 +enable_masking=1 +sw _key_masked=0
Directory	/workspace/40.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/40.kmac_error.2638692040
Short name	T19
Test name
Test status
Simulation time	8953210831 ps
CPU time	154.35 seconds
Started	Jun 04 02:35:03 PM PDT 24
Finished	Jun 04 02:37:38 PM PDT 24
Peak memory	252044 kb
Host	smart-eb8e5ec4-7fb2-4676-8a63-c64d54bb817d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2638692040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.2638692040 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_error/latest

Test location	/workspace/coverage/default/40.kmac_key_error.772103037
Short name	T971
Test name
Test status
Simulation time	6400663531 ps
CPU time	7.89 seconds
Started	Jun 04 02:35:01 PM PDT 24
Finished	Jun 04 02:35:09 PM PDT 24
Peak memory	224388 kb
Host	smart-7d05b83c-f0dd-40f2-8dd6-7e21fdc55619
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=772103037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.772103037 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_key_error/latest

Test location	/workspace/coverage/default/40.kmac_long_msg_and_output.3831319592
Short name	T312
Test name
Test status
Simulation time	44974096262 ps
CPU time	1228.48 seconds
Started	Jun 04 02:34:41 PM PDT 24
Finished	Jun 04 02:55:10 PM PDT 24
Peak memory	329516 kb
Host	smart-8ca5af98-2bc9-40eb-ba0c-ea49bec09e17
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831319592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a nd_output.3831319592 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/40.kmac_sideload.2179547888
Short name	T701
Test name
Test status
Simulation time	14387795795 ps
CPU time	389.89 seconds
Started	Jun 04 02:34:41 PM PDT 24
Finished	Jun 04 02:41:12 PM PDT 24
Peak memory	250268 kb
Host	smart-4c4af6e6-e4f1-41eb-bf41-2378f1ee341d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179547888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.2179547888 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_sideload/latest

Test location	/workspace/coverage/default/40.kmac_smoke.2000850682
Short name	T426
Test name
Test status
Simulation time	30787458149 ps
CPU time	46.41 seconds
Started	Jun 04 02:34:40 PM PDT 24
Finished	Jun 04 02:35:27 PM PDT 24
Peak memory	227436 kb
Host	smart-0b3c56ed-3b71-4222-b1b7-5d3bb61f58d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2000850682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.2000850682 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_smoke/latest

Test location	/workspace/coverage/default/40.kmac_stress_all.979330592
Short name	T1023
Test name
Test status
Simulation time	112112044280 ps
CPU time	983.11 seconds
Started	Jun 04 02:35:09 PM PDT 24
Finished	Jun 04 02:51:33 PM PDT 24
Peak memory	334376 kb
Host	smart-bf5ab5d3-cfc1-48ee-84c0-9992cc908873
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=979330592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.979330592 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_stress_all/latest

Test location	/workspace/coverage/default/40.kmac_stress_all_with_rand_reset.2300134571
Short name	T974
Test name
Test status
Simulation time	94001915264 ps
CPU time	1544.06 seconds
Started	Jun 04 02:35:16 PM PDT 24
Finished	Jun 04 03:01:01 PM PDT 24
Peak memory	325616 kb
Host	smart-54dc17ff-2969-431e-9e71-35948f7b8850
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2300134571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all_with_rand_reset.2300134571 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_kmac.4078711557
Short name	T151
Test name
Test status
Simulation time	120785500 ps
CPU time	6.65 seconds
Started	Jun 04 02:34:56 PM PDT 24
Finished	Jun 04 02:35:03 PM PDT 24
Peak memory	220236 kb
Host	smart-88643f30-4540-4abc-8cb6-447cb35c3fd2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078711557 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.kmac_test_vectors_kmac.4078711557 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_kmac_xof.1669930075
Short name	T531
Test name
Test status
Simulation time	218167961 ps
CPU time	5.86 seconds
Started	Jun 04 02:34:56 PM PDT 24
Finished	Jun 04 02:35:03 PM PDT 24
Peak memory	219344 kb
Host	smart-091668c0-5d3d-407e-9420-b87db83bdac9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669930075 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_kmac_xof.1669930075 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_224.1978470334
Short name	T379
Test name
Test status
Simulation time	354966020628 ps
CPU time	2191.1 seconds
Started	Jun 04 02:34:49 PM PDT 24
Finished	Jun 04 03:11:21 PM PDT 24
Peak memory	401504 kb
Host	smart-c6ca715b-ad28-4d4f-9c9d-e280a1a67169
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1978470334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.1978470334 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_256.684948191
Short name	T574
Test name
Test status
Simulation time	53948872275 ps
CPU time	1720.05 seconds
Started	Jun 04 02:34:50 PM PDT 24
Finished	Jun 04 03:03:31 PM PDT 24
Peak memory	385912 kb
Host	smart-7648654b-cf1a-4f20-894e-93336dc4d46a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=684948191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.684948191 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_384.3092689004
Short name	T870
Test name
Test status
Simulation time	48607124697 ps
CPU time	1710.85 seconds
Started	Jun 04 02:34:49 PM PDT 24
Finished	Jun 04 03:03:20 PM PDT 24
Peak memory	346560 kb
Host	smart-cc2a6c25-7399-4cea-979b-048c4f7903a6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3092689004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.3092689004 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_512.1991824371
Short name	T230
Test name
Test status
Simulation time	124647751894 ps
CPU time	1254.65 seconds
Started	Jun 04 02:34:55 PM PDT 24
Finished	Jun 04 02:55:50 PM PDT 24
Peak memory	305520 kb
Host	smart-751c8151-9237-4a91-9736-c4ff257b03f8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1991824371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.1991824371 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_shake_128.3554975204
Short name	T200
Test name
Test status
Simulation time	677461838813 ps
CPU time	6172.9 seconds
Started	Jun 04 02:34:55 PM PDT 24
Finished	Jun 04 04:17:50 PM PDT 24
Peak memory	647756 kb
Host	smart-f6d6469d-aaeb-4c8d-9254-6fc80eeee551
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3554975204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.3554975204 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_shake_256.3676995012
Short name	T180
Test name
Test status
Simulation time	54845616688 ps
CPU time	4664.65 seconds
Started	Jun 04 02:34:56 PM PDT 24
Finished	Jun 04 03:52:41 PM PDT 24
Peak memory	575136 kb
Host	smart-78d654dd-ca9a-421a-b7c4-92a61cc4f822
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3676995012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.3676995012 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/41.kmac_alert_test.767816730
Short name	T883
Test name
Test status
Simulation time	13439993 ps
CPU time	0.81 seconds
Started	Jun 04 02:35:31 PM PDT 24
Finished	Jun 04 02:35:33 PM PDT 24
Peak memory	218856 kb
Host	smart-17cffcd7-ba10-4aee-a01e-b16abe77b420
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767816730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.767816730 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_alert_test/latest

Test location	/workspace/coverage/default/41.kmac_app.86133821
Short name	T830
Test name
Test status
Simulation time	1318098887 ps
CPU time	11.29 seconds
Started	Jun 04 02:35:23 PM PDT 24
Finished	Jun 04 02:35:34 PM PDT 24
Peak memory	227320 kb
Host	smart-59d32379-f55c-4c95-9b10-9349c7d0740f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=86133821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.86133821 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_app/latest

Test location	/workspace/coverage/default/41.kmac_burst_write.25201269
Short name	T564
Test name
Test status
Simulation time	61647555999 ps
CPU time	615.19 seconds
Started	Jun 04 02:35:18 PM PDT 24
Finished	Jun 04 02:45:34 PM PDT 24
Peak memory	243476 kb
Host	smart-045dc5ea-981d-44cf-b1d2-fb8cca2d54a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=25201269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.25201269 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_burst_write/latest

Test location	/workspace/coverage/default/41.kmac_entropy_refresh.3260403494
Short name	T543
Test name
Test status
Simulation time	19112399087 ps
CPU time	389.96 seconds
Started	Jun 04 02:35:23 PM PDT 24
Finished	Jun 04 02:41:54 PM PDT 24
Peak memory	249776 kb
Host	smart-820345ff-4fdb-409e-9e03-113505b52cd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3260403494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.3260403494 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/41.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/41.kmac_error.294120579
Short name	T361
Test name
Test status
Simulation time	29393639760 ps
CPU time	345.81 seconds
Started	Jun 04 02:35:31 PM PDT 24
Finished	Jun 04 02:41:17 PM PDT 24
Peak memory	259528 kb
Host	smart-19e0fbb8-5f48-44c0-8adc-9fe85291c1e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=294120579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.294120579 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_error/latest

Test location	/workspace/coverage/default/41.kmac_key_error.4052984461
Short name	T288
Test name
Test status
Simulation time	502548986 ps
CPU time	2.81 seconds
Started	Jun 04 02:35:32 PM PDT 24
Finished	Jun 04 02:35:36 PM PDT 24
Peak memory	223228 kb
Host	smart-eb8c737d-5085-41d9-8695-f1aeef3f3717
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4052984461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.4052984461 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_key_error/latest

Test location	/workspace/coverage/default/41.kmac_lc_escalation.780797544
Short name	T48
Test name
Test status
Simulation time	129787832 ps
CPU time	1.52 seconds
Started	Jun 04 02:35:30 PM PDT 24
Finished	Jun 04 02:35:32 PM PDT 24
Peak memory	227288 kb
Host	smart-17bad5cc-7717-4d9d-8595-229af338a13c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780797544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.780797544 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/41.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/41.kmac_long_msg_and_output.4021226810
Short name	T920
Test name
Test status
Simulation time	12291229452 ps
CPU time	394.15 seconds
Started	Jun 04 02:35:19 PM PDT 24
Finished	Jun 04 02:41:53 PM PDT 24
Peak memory	260060 kb
Host	smart-95dd3d3d-bd1c-4c91-ba6d-a73bce5b64f5
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021226810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a nd_output.4021226810 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/41.kmac_sideload.1150694038
Short name	T727
Test name
Test status
Simulation time	3200718285 ps
CPU time	110.21 seconds
Started	Jun 04 02:35:19 PM PDT 24
Finished	Jun 04 02:37:10 PM PDT 24
Peak memory	232320 kb
Host	smart-8bd6a2f5-b066-4899-a6b2-65f09cdf034f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150694038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.1150694038 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_sideload/latest

Test location	/workspace/coverage/default/41.kmac_smoke.1809342558
Short name	T789
Test name
Test status
Simulation time	6388706180 ps
CPU time	62.77 seconds
Started	Jun 04 02:35:18 PM PDT 24
Finished	Jun 04 02:36:21 PM PDT 24
Peak memory	222728 kb
Host	smart-dc660ab6-d55f-4e37-9ea5-015cffadd418
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809342558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.1809342558 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_smoke/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_kmac.3106204874
Short name	T586
Test name
Test status
Simulation time	433073453 ps
CPU time	5.35 seconds
Started	Jun 04 02:35:22 PM PDT 24
Finished	Jun 04 02:35:28 PM PDT 24
Peak memory	219352 kb
Host	smart-bccf4ef5-36bc-48b3-bbf2-a6bf899da852
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106204874 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 41.kmac_test_vectors_kmac.3106204874 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_kmac_xof.1614789404
Short name	T224
Test name
Test status
Simulation time	1013596212 ps
CPU time	6.02 seconds
Started	Jun 04 02:35:25 PM PDT 24
Finished	Jun 04 02:35:31 PM PDT 24
Peak memory	219280 kb
Host	smart-1a0b1075-61b3-4171-8af4-182417db065a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614789404 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_kmac_xof.1614789404 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_224.1454421554
Short name	T977
Test name
Test status
Simulation time	390286249416 ps
CPU time	2479.68 seconds
Started	Jun 04 02:35:24 PM PDT 24
Finished	Jun 04 03:16:44 PM PDT 24
Peak memory	397412 kb
Host	smart-c1f3a8e8-63e8-4261-b7ff-81e2c76c5ff7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1454421554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.1454421554 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_256.1036370224
Short name	T501
Test name
Test status
Simulation time	126119707006 ps
CPU time	2136.34 seconds
Started	Jun 04 02:35:24 PM PDT 24
Finished	Jun 04 03:11:01 PM PDT 24
Peak memory	386928 kb
Host	smart-b17f0ee2-496b-454d-82a6-1cbe063bfad9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1036370224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.1036370224 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_384.664302689
Short name	T326
Test name
Test status
Simulation time	116089370306 ps
CPU time	1485.9 seconds
Started	Jun 04 02:35:24 PM PDT 24
Finished	Jun 04 03:00:11 PM PDT 24
Peak memory	345332 kb
Host	smart-2015153b-553e-4fef-9bbb-3e984c799097
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=664302689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.664302689 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_512.1447691175
Short name	T360
Test name
Test status
Simulation time	42434156219 ps
CPU time	1027.87 seconds
Started	Jun 04 02:35:23 PM PDT 24
Finished	Jun 04 02:52:32 PM PDT 24
Peak memory	303984 kb
Host	smart-a41d2456-8416-401d-a24f-852425c941d2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1447691175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.1447691175 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_shake_128.3946957169
Short name	T497
Test name
Test status
Simulation time	66675351462 ps
CPU time	5338.04 seconds
Started	Jun 04 02:35:24 PM PDT 24
Finished	Jun 04 04:04:23 PM PDT 24
Peak memory	651776 kb
Host	smart-fa874e66-f0bd-4663-bff1-ab2f322f1d65
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3946957169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.3946957169 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_shake_256.436989282
Short name	T613
Test name
Test status
Simulation time	591813192682 ps
CPU time	5013.94 seconds
Started	Jun 04 02:35:23 PM PDT 24
Finished	Jun 04 03:58:59 PM PDT 24
Peak memory	560036 kb
Host	smart-1a146ff6-1c5d-42b2-a099-01f209316e6e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=436989282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.436989282 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/42.kmac_alert_test.2263472397
Short name	T695
Test name
Test status
Simulation time	46608102 ps
CPU time	0.82 seconds
Started	Jun 04 02:35:59 PM PDT 24
Finished	Jun 04 02:36:00 PM PDT 24
Peak memory	218916 kb
Host	smart-eb168541-c5db-4603-9c22-e3637645b825
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263472397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.2263472397 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_alert_test/latest

Test location	/workspace/coverage/default/42.kmac_app.3039970386
Short name	T137
Test name
Test status
Simulation time	7445566423 ps
CPU time	97.16 seconds
Started	Jun 04 02:35:45 PM PDT 24
Finished	Jun 04 02:37:23 PM PDT 24
Peak memory	233196 kb
Host	smart-6021c2b5-df3e-45b7-949c-1a4776472a1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3039970386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.3039970386 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_app/latest

Test location	/workspace/coverage/default/42.kmac_burst_write.648558033
Short name	T828
Test name
Test status
Simulation time	2295523028 ps
CPU time	194.39 seconds
Started	Jun 04 02:35:48 PM PDT 24
Finished	Jun 04 02:39:02 PM PDT 24
Peak memory	243804 kb
Host	smart-7dd6ce8e-a4e6-4b7a-ad4e-433716a88493
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=648558033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.648558033 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_burst_write/latest

Test location	/workspace/coverage/default/42.kmac_entropy_refresh.4140219099
Short name	T18
Test name
Test status
Simulation time	21731023984 ps
CPU time	144.9 seconds
Started	Jun 04 02:35:52 PM PDT 24
Finished	Jun 04 02:38:17 PM PDT 24
Peak memory	238644 kb
Host	smart-cf60e0a5-c2aa-44b9-ae42-e59168b4cbbe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4140219099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.4140219099 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/42.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/42.kmac_error.2974266939
Short name	T995
Test name
Test status
Simulation time	3836136711 ps
CPU time	224.25 seconds
Started	Jun 04 02:35:53 PM PDT 24
Finished	Jun 04 02:39:38 PM PDT 24
Peak memory	253704 kb
Host	smart-c4f78e86-3493-4557-8b53-a214bc14111e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2974266939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.2974266939 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_error/latest

Test location	/workspace/coverage/default/42.kmac_key_error.3738282506
Short name	T623
Test name
Test status
Simulation time	3998529733 ps
CPU time	8.04 seconds
Started	Jun 04 02:35:53 PM PDT 24
Finished	Jun 04 02:36:02 PM PDT 24
Peak memory	225884 kb
Host	smart-395896cd-3f28-4977-aed7-96fc74fef13a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3738282506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.3738282506 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_key_error/latest

Test location	/workspace/coverage/default/42.kmac_lc_escalation.3911265023
Short name	T906
Test name
Test status
Simulation time	45267314 ps
CPU time	1.52 seconds
Started	Jun 04 02:35:53 PM PDT 24
Finished	Jun 04 02:35:55 PM PDT 24
Peak memory	227308 kb
Host	smart-ac4d143b-5083-4d05-b5dc-9cef6f3f72f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3911265023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.3911265023 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/42.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/42.kmac_long_msg_and_output.1216968747
Short name	T348
Test name
Test status
Simulation time	24272203400 ps
CPU time	2395.42 seconds
Started	Jun 04 02:35:39 PM PDT 24
Finished	Jun 04 03:15:35 PM PDT 24
Peak memory	441648 kb
Host	smart-8688a07a-3faa-4ed5-b1b3-96884b4ca50a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216968747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a nd_output.1216968747 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/42.kmac_sideload.3702639844
Short name	T243
Test name
Test status
Simulation time	16935857107 ps
CPU time	258.23 seconds
Started	Jun 04 02:35:38 PM PDT 24
Finished	Jun 04 02:39:57 PM PDT 24
Peak memory	246988 kb
Host	smart-72394317-d804-4f59-8cb4-a472ad383142
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702639844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.3702639844 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_sideload/latest

Test location	/workspace/coverage/default/42.kmac_smoke.2764978203
Short name	T644
Test name
Test status
Simulation time	597097393 ps
CPU time	25.7 seconds
Started	Jun 04 02:35:31 PM PDT 24
Finished	Jun 04 02:35:57 PM PDT 24
Peak memory	221948 kb
Host	smart-c785f6d9-0313-495c-9ab8-d679f6a6a832
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2764978203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.2764978203 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_smoke/latest

Test location	/workspace/coverage/default/42.kmac_stress_all.2846633376
Short name	T1038
Test name
Test status
Simulation time	19763705446 ps
CPU time	1851.69 seconds
Started	Jun 04 02:35:59 PM PDT 24
Finished	Jun 04 03:06:51 PM PDT 24
Peak memory	352864 kb
Host	smart-03fe338e-eadd-4347-b3ad-24e19c110310
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2846633376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2846633376 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_stress_all/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_kmac.1909494363
Short name	T192
Test name
Test status
Simulation time	248560255 ps
CPU time	7.06 seconds
Started	Jun 04 02:35:45 PM PDT 24
Finished	Jun 04 02:35:53 PM PDT 24
Peak memory	219304 kb
Host	smart-9cb673d8-7d1c-46e6-8d63-67f4adc6b342
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909494363 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 42.kmac_test_vectors_kmac.1909494363 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_kmac_xof.206654129
Short name	T419
Test name
Test status
Simulation time	283074334 ps
CPU time	5.88 seconds
Started	Jun 04 02:35:46 PM PDT 24
Finished	Jun 04 02:35:53 PM PDT 24
Peak memory	219240 kb
Host	smart-0be97d5d-2429-4456-921b-a8e67f0b2599
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206654129 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 42.kmac_test_vectors_kmac_xof.206654129 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_224.63762672
Short name	T594
Test name
Test status
Simulation time	236968703136 ps
CPU time	2285.63 seconds
Started	Jun 04 02:35:46 PM PDT 24
Finished	Jun 04 03:13:52 PM PDT 24
Peak memory	388356 kb
Host	smart-94b09f32-a92e-4a3b-86cf-136d44262a53
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=63762672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.63762672 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_256.2247588551
Short name	T741
Test name
Test status
Simulation time	62617444093 ps
CPU time	1794.67 seconds
Started	Jun 04 02:35:44 PM PDT 24
Finished	Jun 04 03:05:39 PM PDT 24
Peak memory	392736 kb
Host	smart-cd92386d-e087-4f7e-a942-b0d15fa5af46
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2247588551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.2247588551 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_384.3597827197
Short name	T444
Test name
Test status
Simulation time	15828848447 ps
CPU time	1384.1 seconds
Started	Jun 04 02:35:45 PM PDT 24
Finished	Jun 04 02:58:49 PM PDT 24
Peak memory	345388 kb
Host	smart-93940478-0f5f-47d1-8936-0623fdfed350
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3597827197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.3597827197 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_512.2318327319
Short name	T1063
Test name
Test status
Simulation time	462044904546 ps
CPU time	1159.88 seconds
Started	Jun 04 02:35:47 PM PDT 24
Finished	Jun 04 02:55:08 PM PDT 24
Peak memory	296996 kb
Host	smart-9a6eed44-1bdc-4b08-a859-564f665abe3f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2318327319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.2318327319 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_shake_128.3723040010
Short name	T270
Test name
Test status
Simulation time	66358588395 ps
CPU time	5193.32 seconds
Started	Jun 04 02:35:44 PM PDT 24
Finished	Jun 04 04:02:18 PM PDT 24
Peak memory	635040 kb
Host	smart-d976c155-a8ff-4d32-ace4-df0496e87f9a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3723040010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.3723040010 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_shake_256.3801458677
Short name	T338
Test name
Test status
Simulation time	437992236530 ps
CPU time	5252.67 seconds
Started	Jun 04 02:35:45 PM PDT 24
Finished	Jun 04 04:03:19 PM PDT 24
Peak memory	549976 kb
Host	smart-31f57cb4-1153-4b46-b165-2e7462b8dfd2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3801458677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.3801458677 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/43.kmac_alert_test.2225276379
Short name	T518
Test name
Test status
Simulation time	40782152 ps
CPU time	0.83 seconds
Started	Jun 04 02:36:24 PM PDT 24
Finished	Jun 04 02:36:25 PM PDT 24
Peak memory	218900 kb
Host	smart-82f7d6e5-0e3b-408b-99d7-22ff0a10e497
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225276379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.2225276379 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_alert_test/latest

Test location	/workspace/coverage/default/43.kmac_app.1075350189
Short name	T637
Test name
Test status
Simulation time	10229329869 ps
CPU time	267.74 seconds
Started	Jun 04 02:36:15 PM PDT 24
Finished	Jun 04 02:40:43 PM PDT 24
Peak memory	244012 kb
Host	smart-e47ca5d8-ad89-4332-a35a-bb496a44d058
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1075350189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.1075350189 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_app/latest

Test location	/workspace/coverage/default/43.kmac_burst_write.937303323
Short name	T143
Test name
Test status
Simulation time	87152870570 ps
CPU time	854.88 seconds
Started	Jun 04 02:36:08 PM PDT 24
Finished	Jun 04 02:50:23 PM PDT 24
Peak memory	243852 kb
Host	smart-d7e94cfe-251d-40dc-b6af-ca7046fb7c38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=937303323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.937303323 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_burst_write/latest

Test location	/workspace/coverage/default/43.kmac_entropy_refresh.3717699162
Short name	T167
Test name
Test status
Simulation time	13230804678 ps
CPU time	388.75 seconds
Started	Jun 04 02:36:15 PM PDT 24
Finished	Jun 04 02:42:44 PM PDT 24
Peak memory	253744 kb
Host	smart-a51bc7cc-4e2f-4b47-ba36-8b944fe404fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3717699162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.3717699162 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/43.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/43.kmac_error.3595948615
Short name	T368
Test name
Test status
Simulation time	3743220261 ps
CPU time	69.69 seconds
Started	Jun 04 02:36:17 PM PDT 24
Finished	Jun 04 02:37:27 PM PDT 24
Peak memory	243912 kb
Host	smart-bcfb8b65-cf44-41ce-a522-96cce1eaeb8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3595948615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.3595948615 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_error/latest

Test location	/workspace/coverage/default/43.kmac_key_error.275207537
Short name	T852
Test name
Test status
Simulation time	296517422 ps
CPU time	3.83 seconds
Started	Jun 04 02:36:25 PM PDT 24
Finished	Jun 04 02:36:29 PM PDT 24
Peak memory	223640 kb
Host	smart-0493e2c0-f56c-488c-ba9c-b0ee23b5d79a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=275207537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.275207537 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_key_error/latest

Test location	/workspace/coverage/default/43.kmac_lc_escalation.1483798910
Short name	T647
Test name
Test status
Simulation time	44446974 ps
CPU time	1.49 seconds
Started	Jun 04 02:36:24 PM PDT 24
Finished	Jun 04 02:36:26 PM PDT 24
Peak memory	227332 kb
Host	smart-c42220c9-b3c1-4952-8938-bc07aee90df5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483798910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.1483798910 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/43.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/43.kmac_long_msg_and_output.1239811792
Short name	T581
Test name
Test status
Simulation time	42458558887 ps
CPU time	3542.45 seconds
Started	Jun 04 02:36:00 PM PDT 24
Finished	Jun 04 03:35:03 PM PDT 24
Peak memory	531580 kb
Host	smart-b00a912b-a723-4a16-873d-ecee7ab94d64
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239811792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a nd_output.1239811792 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/43.kmac_sideload.1297906407
Short name	T620
Test name
Test status
Simulation time	3603661036 ps
CPU time	113.16 seconds
Started	Jun 04 02:36:08 PM PDT 24
Finished	Jun 04 02:38:01 PM PDT 24
Peak memory	233804 kb
Host	smart-b655044a-42c2-4d53-9ae8-9aa5e909cd33
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297906407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.1297906407 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_sideload/latest

Test location	/workspace/coverage/default/43.kmac_smoke.1995335119
Short name	T1052
Test name
Test status
Simulation time	16307131726 ps
CPU time	35.41 seconds
Started	Jun 04 02:36:01 PM PDT 24
Finished	Jun 04 02:36:37 PM PDT 24
Peak memory	227380 kb
Host	smart-48b57598-32e3-4c38-8228-308ddf8fa1e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1995335119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.1995335119 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_smoke/latest

Test location	/workspace/coverage/default/43.kmac_stress_all.4198337010
Short name	T558
Test name
Test status
Simulation time	25057243149 ps
CPU time	432.42 seconds
Started	Jun 04 02:36:25 PM PDT 24
Finished	Jun 04 02:43:38 PM PDT 24
Peak memory	286572 kb
Host	smart-29a3b648-4c23-47b2-9705-ec7e5b822b6f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4198337010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.4198337010 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_stress_all/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_kmac.2223071055
Short name	T530
Test name
Test status
Simulation time	373033413 ps
CPU time	7.01 seconds
Started	Jun 04 02:36:15 PM PDT 24
Finished	Jun 04 02:36:23 PM PDT 24
Peak memory	219268 kb
Host	smart-237a7750-4393-445e-90bc-15ede71cddc9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223071055 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.kmac_test_vectors_kmac.2223071055 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_kmac_xof.269346864
Short name	T801
Test name
Test status
Simulation time	206413422 ps
CPU time	6.37 seconds
Started	Jun 04 02:36:17 PM PDT 24
Finished	Jun 04 02:36:24 PM PDT 24
Peak memory	219320 kb
Host	smart-149f71ac-3b9b-47a8-8ffd-ee01dbed7493
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269346864 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 43.kmac_test_vectors_kmac_xof.269346864 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_224.2131374284
Short name	T258
Test name
Test status
Simulation time	105335363690 ps
CPU time	1906.78 seconds
Started	Jun 04 02:36:06 PM PDT 24
Finished	Jun 04 03:07:54 PM PDT 24
Peak memory	393696 kb
Host	smart-ab7fff0f-e89a-4c61-9345-da59cbc4323e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2131374284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.2131374284 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_256.2519149454
Short name	T217
Test name
Test status
Simulation time	429564423455 ps
CPU time	2265.2 seconds
Started	Jun 04 02:36:06 PM PDT 24
Finished	Jun 04 03:13:52 PM PDT 24
Peak memory	381292 kb
Host	smart-52c008bb-6db4-401a-85d2-c95d774b1321
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2519149454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.2519149454 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_384.4179409490
Short name	T355
Test name
Test status
Simulation time	156479018090 ps
CPU time	1600.68 seconds
Started	Jun 04 02:36:16 PM PDT 24
Finished	Jun 04 03:02:58 PM PDT 24
Peak memory	339128 kb
Host	smart-3d9fe142-ee4b-4877-b1c8-cc16173f2cb8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4179409490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.4179409490 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_512.3149961333
Short name	T905
Test name
Test status
Simulation time	34455091907 ps
CPU time	1166.79 seconds
Started	Jun 04 02:36:18 PM PDT 24
Finished	Jun 04 02:55:45 PM PDT 24
Peak memory	302044 kb
Host	smart-681e125e-34cb-421c-a102-5a8f93663982
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3149961333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.3149961333 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_shake_128.917864563
Short name	T410
Test name
Test status
Simulation time	188789384837 ps
CPU time	5896.54 seconds
Started	Jun 04 02:36:15 PM PDT 24
Finished	Jun 04 04:14:33 PM PDT 24
Peak memory	662168 kb
Host	smart-47f765fa-e514-4b49-8660-9f0875931af9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=917864563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.917864563 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_shake_256.3872496134
Short name	T485
Test name
Test status
Simulation time	245422634688 ps
CPU time	5146.32 seconds
Started	Jun 04 02:36:15 PM PDT 24
Finished	Jun 04 04:02:02 PM PDT 24
Peak memory	574900 kb
Host	smart-046f3940-1e8f-47ad-9db9-617af068b1d1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3872496134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.3872496134 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/44.kmac_alert_test.1635582153
Short name	T365
Test name
Test status
Simulation time	61761914 ps
CPU time	0.91 seconds
Started	Jun 04 02:36:45 PM PDT 24
Finished	Jun 04 02:36:46 PM PDT 24
Peak memory	218860 kb
Host	smart-6d8a0167-fed4-463f-b98b-6a2aced43fd0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635582153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.1635582153 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_alert_test/latest

Test location	/workspace/coverage/default/44.kmac_app.999748621
Short name	T760
Test name
Test status
Simulation time	7444608674 ps
CPU time	428.81 seconds
Started	Jun 04 02:36:37 PM PDT 24
Finished	Jun 04 02:43:47 PM PDT 24
Peak memory	255256 kb
Host	smart-8b5fa541-a69a-425f-963e-1cb1c7de6d59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=999748621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.999748621 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_app/latest

Test location	/workspace/coverage/default/44.kmac_burst_write.1573437628
Short name	T301
Test name
Test status
Simulation time	4272879044 ps
CPU time	40.11 seconds
Started	Jun 04 02:36:29 PM PDT 24
Finished	Jun 04 02:37:10 PM PDT 24
Peak memory	227400 kb
Host	smart-7e178dd1-1217-4578-a7d1-77971c279314
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1573437628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.1573437628 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_burst_write/latest

Test location	/workspace/coverage/default/44.kmac_entropy_refresh.3301164310
Short name	T62
Test name
Test status
Simulation time	83420862612 ps
CPU time	154.33 seconds
Started	Jun 04 02:36:37 PM PDT 24
Finished	Jun 04 02:39:12 PM PDT 24
Peak memory	238528 kb
Host	smart-302c4906-26ac-4ddf-b1b4-9be732377954
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3301164310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.3301164310 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/44.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/44.kmac_error.1993523959
Short name	T654
Test name
Test status
Simulation time	13192794903 ps
CPU time	237.26 seconds
Started	Jun 04 02:36:45 PM PDT 24
Finished	Jun 04 02:40:42 PM PDT 24
Peak memory	253356 kb
Host	smart-40751c5a-43a2-4c3c-9c46-6f5d4a5109d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1993523959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.1993523959 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_error/latest

Test location	/workspace/coverage/default/44.kmac_lc_escalation.1022477602
Short name	T517
Test name
Test status
Simulation time	122041221 ps
CPU time	1.85 seconds
Started	Jun 04 02:36:45 PM PDT 24
Finished	Jun 04 02:36:48 PM PDT 24
Peak memory	227356 kb
Host	smart-5ac9d257-3dc3-4728-b7ca-ef2d40bc99e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022477602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.1022477602 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/44.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/44.kmac_long_msg_and_output.1575128307
Short name	T284
Test name
Test status
Simulation time	31070029486 ps
CPU time	865.7 seconds
Started	Jun 04 02:36:32 PM PDT 24
Finished	Jun 04 02:50:58 PM PDT 24
Peak memory	295244 kb
Host	smart-54748bff-79e8-4f1b-adae-6b8533223a8d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575128307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a nd_output.1575128307 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/44.kmac_sideload.687968275
Short name	T463
Test name
Test status
Simulation time	22901523522 ps
CPU time	513.9 seconds
Started	Jun 04 02:36:33 PM PDT 24
Finished	Jun 04 02:45:07 PM PDT 24
Peak memory	258396 kb
Host	smart-98923fc5-1d7f-4971-9558-86ce8efae42a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687968275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.687968275 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_sideload/latest

Test location	/workspace/coverage/default/44.kmac_smoke.3299512344
Short name	T223
Test name
Test status
Simulation time	6859559284 ps
CPU time	39.57 seconds
Started	Jun 04 02:36:27 PM PDT 24
Finished	Jun 04 02:37:07 PM PDT 24
Peak memory	226760 kb
Host	smart-49cdd0ef-893d-4ad3-98e9-05d03ffa0bfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3299512344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.3299512344 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_smoke/latest

Test location	/workspace/coverage/default/44.kmac_stress_all.1551868533
Short name	T16
Test name
Test status
Simulation time	89336044996 ps
CPU time	1697.83 seconds
Started	Jun 04 02:36:44 PM PDT 24
Finished	Jun 04 03:05:02 PM PDT 24
Peak memory	419776 kb
Host	smart-a47ecd75-9f5c-4550-bc56-df0ecf8a5aff
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1551868533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.1551868533 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_stress_all/latest

Test location	/workspace/coverage/default/44.kmac_stress_all_with_rand_reset.2665048792
Short name	T721
Test name
Test status
Simulation time	452546995864 ps
CPU time	1073.09 seconds
Started	Jun 04 02:36:44 PM PDT 24
Finished	Jun 04 02:54:37 PM PDT 24
Peak memory	309764 kb
Host	smart-538753ef-59f3-4f1a-87dc-5c53535c233f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2665048792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all_with_rand_reset.2665048792 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_kmac.3744280524
Short name	T560
Test name
Test status
Simulation time	201530616 ps
CPU time	5.75 seconds
Started	Jun 04 02:36:36 PM PDT 24
Finished	Jun 04 02:36:42 PM PDT 24
Peak memory	219244 kb
Host	smart-aeab6453-a0c7-4456-a38a-e639f9fb0ea2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744280524 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 44.kmac_test_vectors_kmac.3744280524 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_kmac_xof.2097960696
Short name	T1036
Test name
Test status
Simulation time	137825818 ps
CPU time	6.15 seconds
Started	Jun 04 02:36:38 PM PDT 24
Finished	Jun 04 02:36:45 PM PDT 24
Peak memory	220236 kb
Host	smart-d50b6c58-13d2-4f45-8699-53220481233a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097960696 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_kmac_xof.2097960696 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_224.1499839849
Short name	T306
Test name
Test status
Simulation time	133169666516 ps
CPU time	2071.27 seconds
Started	Jun 04 02:36:31 PM PDT 24
Finished	Jun 04 03:11:03 PM PDT 24
Peak memory	395628 kb
Host	smart-22e0ef21-362d-4209-b365-f85b1e06dfbe
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1499839849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.1499839849 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_256.901098674
Short name	T886
Test name
Test status
Simulation time	19079648867 ps
CPU time	1873.13 seconds
Started	Jun 04 02:36:36 PM PDT 24
Finished	Jun 04 03:07:50 PM PDT 24
Peak memory	377016 kb
Host	smart-e950e2ed-367a-4196-89e6-a83a3cd16c5b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=901098674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.901098674 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_384.2399429353
Short name	T266
Test name
Test status
Simulation time	16780367392 ps
CPU time	1639.85 seconds
Started	Jun 04 02:36:37 PM PDT 24
Finished	Jun 04 03:03:58 PM PDT 24
Peak memory	343116 kb
Host	smart-55d60d08-1faa-4c0a-abc9-3c1972270e32
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2399429353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.2399429353 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_512.4138930507
Short name	T123
Test name
Test status
Simulation time	44623386860 ps
CPU time	1217.92 seconds
Started	Jun 04 02:36:38 PM PDT 24
Finished	Jun 04 02:56:56 PM PDT 24
Peak memory	305132 kb
Host	smart-037d84d5-95e5-4fc7-9e69-4d18deec088a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4138930507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.4138930507 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_shake_128.1296440019
Short name	T616
Test name
Test status
Simulation time	61935325226 ps
CPU time	5345.68 seconds
Started	Jun 04 02:36:38 PM PDT 24
Finished	Jun 04 04:05:45 PM PDT 24
Peak memory	669644 kb
Host	smart-cc6f81a6-3d12-4e6a-a3ad-f1c5c932418c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1296440019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.1296440019 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_shake_256.1143019952
Short name	T425
Test name
Test status
Simulation time	222528840726 ps
CPU time	4887.67 seconds
Started	Jun 04 02:36:37 PM PDT 24
Finished	Jun 04 03:58:06 PM PDT 24
Peak memory	584256 kb
Host	smart-083f6ddf-78bd-4143-a995-d68cd636364f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1143019952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.1143019952 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/45.kmac_alert_test.2822945426
Short name	T638
Test name
Test status
Simulation time	38179010 ps
CPU time	0.82 seconds
Started	Jun 04 02:37:20 PM PDT 24
Finished	Jun 04 02:37:22 PM PDT 24
Peak memory	218920 kb
Host	smart-da25bdff-e673-4252-80e9-f9d49ecb7515
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822945426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.2822945426 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_alert_test/latest

Test location	/workspace/coverage/default/45.kmac_app.2295878176
Short name	T636
Test name
Test status
Simulation time	1715049692 ps
CPU time	17.71 seconds
Started	Jun 04 02:37:04 PM PDT 24
Finished	Jun 04 02:37:22 PM PDT 24
Peak memory	227376 kb
Host	smart-831ef916-b5e2-4216-8fcb-c2932bf8a4f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2295878176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2295878176 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_app/latest

Test location	/workspace/coverage/default/45.kmac_burst_write.560275884
Short name	T865
Test name
Test status
Simulation time	27033044724 ps
CPU time	1106.53 seconds
Started	Jun 04 02:36:51 PM PDT 24
Finished	Jun 04 02:55:19 PM PDT 24
Peak memory	240016 kb
Host	smart-1247ffc6-7a9a-40f4-b15d-ebdc46a79bad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=560275884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.560275884 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_burst_write/latest

Test location	/workspace/coverage/default/45.kmac_entropy_refresh.2511011293
Short name	T681
Test name
Test status
Simulation time	3976996011 ps
CPU time	157.7 seconds
Started	Jun 04 02:37:05 PM PDT 24
Finished	Jun 04 02:39:43 PM PDT 24
Peak memory	239340 kb
Host	smart-df80ebd3-9cb0-4eda-bc35-83eb2a6f7f7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2511011293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.2511011293 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/45.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/45.kmac_error.3522165655
Short name	T699
Test name
Test status
Simulation time	36048196809 ps
CPU time	296.23 seconds
Started	Jun 04 02:37:08 PM PDT 24
Finished	Jun 04 02:42:05 PM PDT 24
Peak memory	257408 kb
Host	smart-72a330e4-420a-4d40-8cfb-43c72c23082b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3522165655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.3522165655 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_error/latest

Test location	/workspace/coverage/default/45.kmac_key_error.3305987837
Short name	T1007
Test name
Test status
Simulation time	2006202200 ps
CPU time	4.65 seconds
Started	Jun 04 02:37:08 PM PDT 24
Finished	Jun 04 02:37:13 PM PDT 24
Peak memory	223824 kb
Host	smart-f3cfd045-39a5-433b-b02c-11f9a91f3bad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3305987837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.3305987837 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_key_error/latest

Test location	/workspace/coverage/default/45.kmac_lc_escalation.3613920679
Short name	T117
Test name
Test status
Simulation time	57277226 ps
CPU time	1.27 seconds
Started	Jun 04 02:37:05 PM PDT 24
Finished	Jun 04 02:37:07 PM PDT 24
Peak memory	227312 kb
Host	smart-2cd4d1ea-f01d-44f7-ad3b-a64c2f8a98a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3613920679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.3613920679 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/45.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/45.kmac_long_msg_and_output.3181634462
Short name	T996
Test name
Test status
Simulation time	56995092867 ps
CPU time	1807.08 seconds
Started	Jun 04 02:36:52 PM PDT 24
Finished	Jun 04 03:06:59 PM PDT 24
Peak memory	381456 kb
Host	smart-5858c87e-cac1-4ed6-80b7-12eea61b229a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181634462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a nd_output.3181634462 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/45.kmac_sideload.385840778
Short name	T1009
Test name
Test status
Simulation time	2872714805 ps
CPU time	98.58 seconds
Started	Jun 04 02:36:52 PM PDT 24
Finished	Jun 04 02:38:31 PM PDT 24
Peak memory	232624 kb
Host	smart-1709be3e-3ef2-4904-ba95-5bc259f8bf18
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385840778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.385840778 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_sideload/latest

Test location	/workspace/coverage/default/45.kmac_smoke.1479575700
Short name	T547
Test name
Test status
Simulation time	1488940323 ps
CPU time	32.6 seconds
Started	Jun 04 02:36:51 PM PDT 24
Finished	Jun 04 02:37:24 PM PDT 24
Peak memory	219404 kb
Host	smart-dbf0fa81-d0e3-448f-be65-967d854e06fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1479575700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.1479575700 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_smoke/latest

Test location	/workspace/coverage/default/45.kmac_stress_all.1324145480
Short name	T521
Test name
Test status
Simulation time	40330589934 ps
CPU time	750.18 seconds
Started	Jun 04 02:37:20 PM PDT 24
Finished	Jun 04 02:49:51 PM PDT 24
Peak memory	330952 kb
Host	smart-c0f81ee5-1b87-44c4-b104-5b382ecb8547
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1324145480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.1324145480 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_stress_all/latest

Test location	/workspace/coverage/default/45.kmac_stress_all_with_rand_reset.2919136099
Short name	T1010
Test name
Test status
Simulation time	89345742043 ps
CPU time	1746.59 seconds
Started	Jun 04 02:37:21 PM PDT 24
Finished	Jun 04 03:06:28 PM PDT 24
Peak memory	303084 kb
Host	smart-4ee52418-18ec-49d0-8aa6-2d5655ad6973
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2919136099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all_with_rand_reset.2919136099 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_kmac.1069510028
Short name	T848
Test name
Test status
Simulation time	895695786 ps
CPU time	6.77 seconds
Started	Jun 04 02:37:05 PM PDT 24
Finished	Jun 04 02:37:12 PM PDT 24
Peak memory	219232 kb
Host	smart-a52e4d1f-928b-43a6-9b1f-cd0768280a4a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069510028 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.kmac_test_vectors_kmac.1069510028 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_kmac_xof.3950762848
Short name	T33
Test name
Test status
Simulation time	2231008061 ps
CPU time	6.86 seconds
Started	Jun 04 02:37:07 PM PDT 24
Finished	Jun 04 02:37:14 PM PDT 24
Peak memory	219476 kb
Host	smart-21d13000-7f3f-4425-a7b6-874f6f926296
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950762848 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_kmac_xof.3950762848 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_224.3673225171
Short name	T809
Test name
Test status
Simulation time	263619359561 ps
CPU time	2138.39 seconds
Started	Jun 04 02:36:59 PM PDT 24
Finished	Jun 04 03:12:38 PM PDT 24
Peak memory	400220 kb
Host	smart-0b87e3af-a4d8-4ea5-ab2e-baf7aff03470
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3673225171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.3673225171 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_256.152274939
Short name	T311
Test name
Test status
Simulation time	252332220295 ps
CPU time	1892.8 seconds
Started	Jun 04 02:36:58 PM PDT 24
Finished	Jun 04 03:08:32 PM PDT 24
Peak memory	379296 kb
Host	smart-75216b65-6ec4-4a7c-a374-dc9c891ec183
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=152274939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.152274939 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_384.2656064749
Short name	T522
Test name
Test status
Simulation time	15522924774 ps
CPU time	1440.93 seconds
Started	Jun 04 02:37:05 PM PDT 24
Finished	Jun 04 03:01:06 PM PDT 24
Peak memory	339024 kb
Host	smart-85752b32-ce2d-4f90-8fb7-53cb5ce9018c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2656064749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.2656064749 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_512.602322880
Short name	T393
Test name
Test status
Simulation time	37076038777 ps
CPU time	1231.47 seconds
Started	Jun 04 02:37:08 PM PDT 24
Finished	Jun 04 02:57:40 PM PDT 24
Peak memory	299928 kb
Host	smart-80365b5c-c386-4311-87a1-9755a4436e19
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=602322880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.602322880 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_shake_128.3698400865
Short name	T726
Test name
Test status
Simulation time	59217792058 ps
CPU time	4971.11 seconds
Started	Jun 04 02:37:09 PM PDT 24
Finished	Jun 04 04:00:02 PM PDT 24
Peak memory	637808 kb
Host	smart-86afa539-c0d8-47b6-8ef6-9d107b8cc42e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3698400865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.3698400865 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_shake_256.1017429804
Short name	T536
Test name
Test status
Simulation time	478132812866 ps
CPU time	4635.99 seconds
Started	Jun 04 02:37:05 PM PDT 24
Finished	Jun 04 03:54:22 PM PDT 24
Peak memory	578108 kb
Host	smart-e5ef1d07-1c9f-4f19-9007-a58c639e7416
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1017429804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.1017429804 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/46.kmac_alert_test.3531803194
Short name	T856
Test name
Test status
Simulation time	26329050 ps
CPU time	0.82 seconds
Started	Jun 04 02:37:47 PM PDT 24
Finished	Jun 04 02:37:49 PM PDT 24
Peak memory	218912 kb
Host	smart-62c6c87a-674f-47f6-90de-e54990569a83
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531803194 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3531803194 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_alert_test/latest

Test location	/workspace/coverage/default/46.kmac_app.4017054577
Short name	T749
Test name
Test status
Simulation time	703001963 ps
CPU time	11.43 seconds
Started	Jun 04 02:37:41 PM PDT 24
Finished	Jun 04 02:37:53 PM PDT 24
Peak memory	227384 kb
Host	smart-6f362051-2a54-4a76-a584-0b77904f8d52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017054577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.4017054577 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_app/latest

Test location	/workspace/coverage/default/46.kmac_burst_write.3907932063
Short name	T1034
Test name
Test status
Simulation time	12614079438 ps
CPU time	317.13 seconds
Started	Jun 04 02:37:19 PM PDT 24
Finished	Jun 04 02:42:37 PM PDT 24
Peak memory	230700 kb
Host	smart-039a7679-dba7-486f-a240-47657f810f19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3907932063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.3907932063 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_burst_write/latest

Test location	/workspace/coverage/default/46.kmac_entropy_refresh.1458388702
Short name	T17
Test name
Test status
Simulation time	7773064775 ps
CPU time	158.3 seconds
Started	Jun 04 02:37:41 PM PDT 24
Finished	Jun 04 02:40:20 PM PDT 24
Peak memory	240500 kb
Host	smart-5d5cff73-a787-4240-80da-75f10b728c07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1458388702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.1458388702 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/46.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/46.kmac_error.716190211
Short name	T460
Test name
Test status
Simulation time	36832123945 ps
CPU time	483.68 seconds
Started	Jun 04 02:37:41 PM PDT 24
Finished	Jun 04 02:45:45 PM PDT 24
Peak memory	268508 kb
Host	smart-7fe61a80-0ecb-4ef1-a955-c3f1bb6998f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=716190211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.716190211 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_error/latest

Test location	/workspace/coverage/default/46.kmac_key_error.4137051075
Short name	T119
Test name
Test status
Simulation time	1723044834 ps
CPU time	13.18 seconds
Started	Jun 04 02:37:49 PM PDT 24
Finished	Jun 04 02:38:03 PM PDT 24
Peak memory	224828 kb
Host	smart-84e08e25-9505-455c-88a9-d0480077c47c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4137051075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.4137051075 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_key_error/latest

Test location	/workspace/coverage/default/46.kmac_lc_escalation.4064015541
Short name	T831
Test name
Test status
Simulation time	30909885 ps
CPU time	1.46 seconds
Started	Jun 04 02:37:47 PM PDT 24
Finished	Jun 04 02:37:50 PM PDT 24
Peak memory	227316 kb
Host	smart-f73ab9f4-5849-4d4b-ac56-8802313dd412
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4064015541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.4064015541 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/46.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/46.kmac_long_msg_and_output.1684934467
Short name	T1073
Test name
Test status
Simulation time	92751215519 ps
CPU time	1241.45 seconds
Started	Jun 04 02:37:22 PM PDT 24
Finished	Jun 04 02:58:04 PM PDT 24
Peak memory	313548 kb
Host	smart-78f0a9dc-247a-4f5a-9a01-7dbb3bed1fcf
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684934467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a nd_output.1684934467 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/46.kmac_sideload.868845271
Short name	T351
Test name
Test status
Simulation time	1908440265 ps
CPU time	155.18 seconds
Started	Jun 04 02:37:19 PM PDT 24
Finished	Jun 04 02:39:55 PM PDT 24
Peak memory	236160 kb
Host	smart-b28b9fbc-8b6e-4f6e-86bf-e40c18358533
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868845271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.868845271 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_sideload/latest

Test location	/workspace/coverage/default/46.kmac_smoke.2620994274
Short name	T519
Test name
Test status
Simulation time	232066711 ps
CPU time	3.73 seconds
Started	Jun 04 02:37:20 PM PDT 24
Finished	Jun 04 02:37:25 PM PDT 24
Peak memory	220160 kb
Host	smart-88d6306a-64c9-4b70-a027-a04703f2ee19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2620994274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2620994274 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_smoke/latest

Test location	/workspace/coverage/default/46.kmac_stress_all.4067206521
Short name	T877
Test name
Test status
Simulation time	109561303956 ps
CPU time	1440.75 seconds
Started	Jun 04 02:37:47 PM PDT 24
Finished	Jun 04 03:01:49 PM PDT 24
Peak memory	396864 kb
Host	smart-d5c0c4f0-859a-49af-b1aa-f33aeaad924f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4067206521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.4067206521 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_stress_all/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_kmac.1127781287
Short name	T472
Test name
Test status
Simulation time	211715605 ps
CPU time	6.83 seconds
Started	Jun 04 02:37:32 PM PDT 24
Finished	Jun 04 02:37:40 PM PDT 24
Peak memory	219224 kb
Host	smart-365c4a7f-5cf0-499c-b865-dcd21d470353
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127781287 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 46.kmac_test_vectors_kmac.1127781287 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_kmac_xof.1464601412
Short name	T1060
Test name
Test status
Simulation time	1909274534 ps
CPU time	6.43 seconds
Started	Jun 04 02:37:34 PM PDT 24
Finished	Jun 04 02:37:41 PM PDT 24
Peak memory	219236 kb
Host	smart-09df14ef-e9d3-489f-992a-f7b28c7cf50e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464601412 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_kmac_xof.1464601412 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_224.1377739275
Short name	T849
Test name
Test status
Simulation time	446850418174 ps
CPU time	2420.39 seconds
Started	Jun 04 02:37:20 PM PDT 24
Finished	Jun 04 03:17:42 PM PDT 24
Peak memory	384688 kb
Host	smart-55ab07ce-1f3a-4349-a087-5a134430f633
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1377739275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.1377739275 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_256.1626782433
Short name	T275
Test name
Test status
Simulation time	112605314783 ps
CPU time	1896.05 seconds
Started	Jun 04 02:37:27 PM PDT 24
Finished	Jun 04 03:09:04 PM PDT 24
Peak memory	388432 kb
Host	smart-d3bf1557-1751-485c-875c-2cd75bfeaf03
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1626782433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.1626782433 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_384.3245602188
Short name	T859
Test name
Test status
Simulation time	148945128276 ps
CPU time	1923.1 seconds
Started	Jun 04 02:37:27 PM PDT 24
Finished	Jun 04 03:09:30 PM PDT 24
Peak memory	345636 kb
Host	smart-8922ff6a-7113-4a84-aec0-33a789106e8f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3245602188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.3245602188 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_512.2956004091
Short name	T1046
Test name
Test status
Simulation time	10727400971 ps
CPU time	1143.16 seconds
Started	Jun 04 02:37:26 PM PDT 24
Finished	Jun 04 02:56:30 PM PDT 24
Peak memory	304408 kb
Host	smart-423f509a-77df-4c36-9341-2c2b0bf8df80
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2956004091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.2956004091 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_shake_128.2319404623
Short name	T182
Test name
Test status
Simulation time	3739617509089 ps
CPU time	6183.71 seconds
Started	Jun 04 02:37:28 PM PDT 24
Finished	Jun 04 04:20:34 PM PDT 24
Peak memory	665968 kb
Host	smart-98d22762-b333-4057-83b0-538cfadda72b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2319404623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.2319404623 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_shake_256.1618781470
Short name	T339
Test name
Test status
Simulation time	153172828997 ps
CPU time	5062.92 seconds
Started	Jun 04 02:37:27 PM PDT 24
Finished	Jun 04 04:01:52 PM PDT 24
Peak memory	577236 kb
Host	smart-df3ed173-febb-4e59-854d-8e2c54a60091
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1618781470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.1618781470 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/47.kmac_alert_test.848967425
Short name	T878
Test name
Test status
Simulation time	21541829 ps
CPU time	0.8 seconds
Started	Jun 04 02:38:18 PM PDT 24
Finished	Jun 04 02:38:20 PM PDT 24
Peak memory	218872 kb
Host	smart-46972064-728d-4e2f-9ac0-a8f59ed7dfd0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848967425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.848967425 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_alert_test/latest

Test location	/workspace/coverage/default/47.kmac_app.3723059588
Short name	T8
Test name
Test status
Simulation time	7062734746 ps
CPU time	141.49 seconds
Started	Jun 04 02:38:01 PM PDT 24
Finished	Jun 04 02:40:23 PM PDT 24
Peak memory	237356 kb
Host	smart-9b7ecb3c-6872-4cbd-b908-8f4a694e7ff9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3723059588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.3723059588 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_app/latest

Test location	/workspace/coverage/default/47.kmac_burst_write.666467700
Short name	T889
Test name
Test status
Simulation time	6126436283 ps
CPU time	257.39 seconds
Started	Jun 04 02:37:56 PM PDT 24
Finished	Jun 04 02:42:14 PM PDT 24
Peak memory	235672 kb
Host	smart-024fe026-9d12-449a-b06d-fbcfec0bd95f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=666467700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.666467700 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_burst_write/latest

Test location	/workspace/coverage/default/47.kmac_entropy_refresh.2761191956
Short name	T829
Test name
Test status
Simulation time	9691875118 ps
CPU time	244.55 seconds
Started	Jun 04 02:38:10 PM PDT 24
Finished	Jun 04 02:42:15 PM PDT 24
Peak memory	244824 kb
Host	smart-1655d4ae-f335-4bc2-a25d-f93da77a1f05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2761191956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.2761191956 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/47.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/47.kmac_error.3242521651
Short name	T1014
Test name
Test status
Simulation time	7969793631 ps
CPU time	99.1 seconds
Started	Jun 04 02:38:10 PM PDT 24
Finished	Jun 04 02:39:50 PM PDT 24
Peak memory	243884 kb
Host	smart-795a8047-793d-4bef-a345-fb4823f06d8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3242521651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.3242521651 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_error/latest

Test location	/workspace/coverage/default/47.kmac_key_error.3437185915
Short name	T356
Test name
Test status
Simulation time	388966705 ps
CPU time	3.38 seconds
Started	Jun 04 02:38:10 PM PDT 24
Finished	Jun 04 02:38:14 PM PDT 24
Peak memory	223156 kb
Host	smart-0e6d5aaf-b316-416e-8779-63dd16527da2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3437185915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.3437185915 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_key_error/latest

Test location	/workspace/coverage/default/47.kmac_lc_escalation.365951797
Short name	T76
Test name
Test status
Simulation time	123638786 ps
CPU time	1.42 seconds
Started	Jun 04 02:38:09 PM PDT 24
Finished	Jun 04 02:38:11 PM PDT 24
Peak memory	227300 kb
Host	smart-51421330-b24e-444d-b24e-8e19cf2ffbc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=365951797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.365951797 +enable_masking=1 +sw_key _masked=0
Directory	/workspace/47.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/47.kmac_long_msg_and_output.3558182397
Short name	T947
Test name
Test status
Simulation time	98190222394 ps
CPU time	2686.92 seconds
Started	Jun 04 02:37:57 PM PDT 24
Finished	Jun 04 03:22:44 PM PDT 24
Peak memory	421328 kb
Host	smart-38d6b4a7-da65-4479-8f60-9378f8e33436
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558182397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a nd_output.3558182397 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/47.kmac_sideload.3888122476
Short name	T487
Test name
Test status
Simulation time	15357470098 ps
CPU time	107.99 seconds
Started	Jun 04 02:37:55 PM PDT 24
Finished	Jun 04 02:39:44 PM PDT 24
Peak memory	236732 kb
Host	smart-02d088e9-825a-4b4f-b4bb-aa82ef3a6f6a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888122476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.3888122476 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_sideload/latest

Test location	/workspace/coverage/default/47.kmac_smoke.1273026249
Short name	T242
Test name
Test status
Simulation time	1868498243 ps
CPU time	20.33 seconds
Started	Jun 04 02:37:48 PM PDT 24
Finished	Jun 04 02:38:09 PM PDT 24
Peak memory	223664 kb
Host	smart-5d500d09-9f3f-4716-93a3-2a9260df53b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1273026249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.1273026249 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_smoke/latest

Test location	/workspace/coverage/default/47.kmac_stress_all.1780790783
Short name	T609
Test name
Test status
Simulation time	11413728890 ps
CPU time	310.9 seconds
Started	Jun 04 02:38:09 PM PDT 24
Finished	Jun 04 02:43:21 PM PDT 24
Peak memory	269488 kb
Host	smart-8768f959-89da-41b5-a0a8-a632fac64e5d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1780790783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.1780790783 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_stress_all/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_kmac.1815307419
Short name	T239
Test name
Test status
Simulation time	431485956 ps
CPU time	5.5 seconds
Started	Jun 04 02:38:00 PM PDT 24
Finished	Jun 04 02:38:06 PM PDT 24
Peak memory	219328 kb
Host	smart-589be34b-620b-4935-a502-3a42b1382f53
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815307419 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.kmac_test_vectors_kmac.1815307419 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_kmac_xof.4089441623
Short name	T478
Test name
Test status
Simulation time	213264293 ps
CPU time	6.42 seconds
Started	Jun 04 02:38:01 PM PDT 24
Finished	Jun 04 02:38:08 PM PDT 24
Peak memory	219284 kb
Host	smart-c74a045a-489e-490f-820b-867b074f6ff4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089441623 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_kmac_xof.4089441623 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_224.1174801132
Short name	T495
Test name
Test status
Simulation time	20225043600 ps
CPU time	2027.19 seconds
Started	Jun 04 02:37:56 PM PDT 24
Finished	Jun 04 03:11:44 PM PDT 24
Peak memory	390004 kb
Host	smart-be467019-ab98-40c8-b457-69ffd42714d3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1174801132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.1174801132 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_256.723559903
Short name	T929
Test name
Test status
Simulation time	95161883883 ps
CPU time	2295.96 seconds
Started	Jun 04 02:37:56 PM PDT 24
Finished	Jun 04 03:16:13 PM PDT 24
Peak memory	393596 kb
Host	smart-2c3e0f4b-ce2c-48f8-bf68-4bdf593af4f6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=723559903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.723559903 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_384.589225685
Short name	T585
Test name
Test status
Simulation time	49551817606 ps
CPU time	1610.3 seconds
Started	Jun 04 02:38:01 PM PDT 24
Finished	Jun 04 03:04:52 PM PDT 24
Peak memory	342028 kb
Host	smart-f1e59ffc-a4ba-4b0e-bdf1-6cec43222630
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=589225685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.589225685 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_512.84928798
Short name	T617
Test name
Test status
Simulation time	40466313224 ps
CPU time	1147.4 seconds
Started	Jun 04 02:38:02 PM PDT 24
Finished	Jun 04 02:57:10 PM PDT 24
Peak memory	308524 kb
Host	smart-b893141a-250e-43a6-ab47-b7cc38ccfa05
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=84928798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.84928798 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_shake_128.3731331509
Short name	T227
Test name
Test status
Simulation time	249721650883 ps
CPU time	5313.88 seconds
Started	Jun 04 02:38:02 PM PDT 24
Finished	Jun 04 04:06:38 PM PDT 24
Peak memory	651308 kb
Host	smart-1a3d5cc7-7d9c-417b-91e2-850ea132728b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3731331509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.3731331509 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_shake_256.815489967
Short name	T58
Test name
Test status
Simulation time	155958365545 ps
CPU time	5156.93 seconds
Started	Jun 04 02:38:10 PM PDT 24
Finished	Jun 04 04:04:08 PM PDT 24
Peak memory	570452 kb
Host	smart-3829db6b-b32c-4588-bd96-beac3a383caa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=815489967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.815489967 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/48.kmac_alert_test.946301390
Short name	T310
Test name
Test status
Simulation time	16093756 ps
CPU time	0.85 seconds
Started	Jun 04 02:38:51 PM PDT 24
Finished	Jun 04 02:38:52 PM PDT 24
Peak memory	218936 kb
Host	smart-1f13f59d-634e-4488-85a2-76899b4bd00e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946301390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.946301390 +enable_m asking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_alert_test/latest

Test location	/workspace/coverage/default/48.kmac_app.1532343023
Short name	T428
Test name
Test status
Simulation time	4106111287 ps
CPU time	25.73 seconds
Started	Jun 04 02:38:43 PM PDT 24
Finished	Jun 04 02:39:09 PM PDT 24
Peak memory	227444 kb
Host	smart-dd676621-0168-4cf8-9983-1fbcda33f420
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1532343023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1532343023 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_app/latest

Test location	/workspace/coverage/default/48.kmac_burst_write.3700192729
Short name	T710
Test name
Test status
Simulation time	25107385753 ps
CPU time	463.79 seconds
Started	Jun 04 02:38:35 PM PDT 24
Finished	Jun 04 02:46:20 PM PDT 24
Peak memory	240488 kb
Host	smart-b8777a83-94ed-41a2-aff4-d0c0601dd0e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3700192729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.3700192729 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_burst_write/latest

Test location	/workspace/coverage/default/48.kmac_entropy_refresh.2796304654
Short name	T385
Test name
Test status
Simulation time	6290764227 ps
CPU time	138.93 seconds
Started	Jun 04 02:38:42 PM PDT 24
Finished	Jun 04 02:41:01 PM PDT 24
Peak memory	238436 kb
Host	smart-4efda8b4-1533-4fd3-af5f-a5a493a8660e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2796304654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.2796304654 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/48.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/48.kmac_error.3183057913
Short name	T381
Test name
Test status
Simulation time	19055754272 ps
CPU time	191.79 seconds
Started	Jun 04 02:38:43 PM PDT 24
Finished	Jun 04 02:41:55 PM PDT 24
Peak memory	259264 kb
Host	smart-e47edcf6-5385-48e5-9ee3-30852fe39e0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3183057913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.3183057913 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_error/latest

Test location	/workspace/coverage/default/48.kmac_key_error.3584082415
Short name	T754
Test name
Test status
Simulation time	5609606158 ps
CPU time	8.61 seconds
Started	Jun 04 02:38:43 PM PDT 24
Finished	Jun 04 02:38:53 PM PDT 24
Peak memory	224636 kb
Host	smart-03eeecda-8e37-456b-8159-600ea58ef3a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584082415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3584082415 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_key_error/latest

Test location	/workspace/coverage/default/48.kmac_lc_escalation.2239862109
Short name	T949
Test name
Test status
Simulation time	55066797 ps
CPU time	1.26 seconds
Started	Jun 04 02:38:44 PM PDT 24
Finished	Jun 04 02:38:46 PM PDT 24
Peak memory	227316 kb
Host	smart-ae2f36af-e8f5-44d3-94cc-39535450e62b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2239862109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.2239862109 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/48.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/48.kmac_long_msg_and_output.1488937105
Short name	T237
Test name
Test status
Simulation time	75932700648 ps
CPU time	2110.83 seconds
Started	Jun 04 02:38:27 PM PDT 24
Finished	Jun 04 03:13:39 PM PDT 24
Peak memory	392752 kb
Host	smart-c02cd805-ea44-4ed9-ae21-06c5f39a508f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488937105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a nd_output.1488937105 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/48.kmac_sideload.3177957973
Short name	T921
Test name
Test status
Simulation time	19752643742 ps
CPU time	298.53 seconds
Started	Jun 04 02:38:27 PM PDT 24
Finished	Jun 04 02:43:26 PM PDT 24
Peak memory	245888 kb
Host	smart-986ed46f-40e6-4d2b-87e9-434dfabf2915
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177957973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3177957973 +e nable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_sideload/latest

Test location	/workspace/coverage/default/48.kmac_smoke.4083349878
Short name	T1059
Test name
Test status
Simulation time	9469118509 ps
CPU time	12.43 seconds
Started	Jun 04 02:38:16 PM PDT 24
Finished	Jun 04 02:38:29 PM PDT 24
Peak memory	227164 kb
Host	smart-23c5337b-a7db-4041-9725-72943fbb45bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4083349878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.4083349878 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_smoke/latest

Test location	/workspace/coverage/default/48.kmac_stress_all.3506821765
Short name	T610
Test name
Test status
Simulation time	12858339152 ps
CPU time	591.25 seconds
Started	Jun 04 02:38:44 PM PDT 24
Finished	Jun 04 02:48:36 PM PDT 24
Peak memory	286492 kb
Host	smart-b5d386d6-24e7-4b10-ab6d-441ce1b3ca7d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3506821765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.3506821765 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_stress_all/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_kmac.3357532416
Short name	T271
Test name
Test status
Simulation time	114031879 ps
CPU time	6.19 seconds
Started	Jun 04 02:38:43 PM PDT 24
Finished	Jun 04 02:38:50 PM PDT 24
Peak memory	219228 kb
Host	smart-e1d9e2e5-28e9-4253-b768-27c48f9d3aa3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357532416 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.kmac_test_vectors_kmac.3357532416 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_kmac_xof.1329944535
Short name	T791
Test name
Test status
Simulation time	188874103 ps
CPU time	5.96 seconds
Started	Jun 04 02:38:44 PM PDT 24
Finished	Jun 04 02:38:50 PM PDT 24
Peak memory	219284 kb
Host	smart-d0bfe821-5a18-47e9-a8bb-381e52bea924
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329944535 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_kmac_xof.1329944535 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_224.3192656866
Short name	T840
Test name
Test status
Simulation time	31067868658 ps
CPU time	1903.47 seconds
Started	Jun 04 02:38:35 PM PDT 24
Finished	Jun 04 03:10:20 PM PDT 24
Peak memory	401984 kb
Host	smart-075e6fb8-61dd-4bc1-9081-76b9c5bd90b0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3192656866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.3192656866 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_256.187866561
Short name	T853
Test name
Test status
Simulation time	256818305488 ps
CPU time	2029.54 seconds
Started	Jun 04 02:38:35 PM PDT 24
Finished	Jun 04 03:12:25 PM PDT 24
Peak memory	386500 kb
Host	smart-908ec51e-2237-4744-b019-7ba5c8496b41
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=187866561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.187866561 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_384.584607293
Short name	T191
Test name
Test status
Simulation time	196437910227 ps
CPU time	1699.72 seconds
Started	Jun 04 02:38:35 PM PDT 24
Finished	Jun 04 03:06:56 PM PDT 24
Peak memory	340448 kb
Host	smart-ab995d5b-99c5-4f2d-bb58-a14cdac45c54
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=584607293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.584607293 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_512.1456159619
Short name	T503
Test name
Test status
Simulation time	131288706716 ps
CPU time	1198.65 seconds
Started	Jun 04 02:38:37 PM PDT 24
Finished	Jun 04 02:58:37 PM PDT 24
Peak memory	298120 kb
Host	smart-61937afc-6cba-47a6-8da4-f99ab7ba993c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1456159619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.1456159619 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_shake_128.710674477
Short name	T296
Test name
Test status
Simulation time	226214729620 ps
CPU time	5365.23 seconds
Started	Jun 04 02:38:36 PM PDT 24
Finished	Jun 04 04:08:02 PM PDT 24
Peak memory	654908 kb
Host	smart-50ed47f5-71d3-4de6-9683-8405de3205ab
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=710674477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.710674477 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_shake_256.1165276412
Short name	T725
Test name
Test status
Simulation time	205655857525 ps
CPU time	4700.5 seconds
Started	Jun 04 02:38:35 PM PDT 24
Finished	Jun 04 03:56:57 PM PDT 24
Peak memory	554500 kb
Host	smart-8f3976a5-ac72-4ca0-9415-a76e41a94483
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1165276412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.1165276412 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/49.kmac_alert_test.3651363015
Short name	T976
Test name
Test status
Simulation time	31125990 ps
CPU time	0.82 seconds
Started	Jun 04 02:39:28 PM PDT 24
Finished	Jun 04 02:39:29 PM PDT 24
Peak memory	218940 kb
Host	smart-fa7e57ec-4dfa-40af-aaed-7d5a83d5e1f4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651363015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3651363015 +enable _masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_alert_test/latest

Test location	/workspace/coverage/default/49.kmac_app.257939435
Short name	T744
Test name
Test status
Simulation time	848501631 ps
CPU time	17.98 seconds
Started	Jun 04 02:39:03 PM PDT 24
Finished	Jun 04 02:39:22 PM PDT 24
Peak memory	227368 kb
Host	smart-8812b534-6762-488b-b47d-6c8fedde038b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=257939435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.257939435 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_app/latest

Test location	/workspace/coverage/default/49.kmac_burst_write.175551571
Short name	T632
Test name
Test status
Simulation time	71484185268 ps
CPU time	1291.68 seconds
Started	Jun 04 02:38:57 PM PDT 24
Finished	Jun 04 03:00:30 PM PDT 24
Peak memory	240224 kb
Host	smart-d25bab2a-f2cf-4680-ad60-ee03ac0522ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=175551571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.175551571 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_burst_write/latest

Test location	/workspace/coverage/default/49.kmac_entropy_refresh.3584201244
Short name	T578
Test name
Test status
Simulation time	33642576527 ps
CPU time	254.46 seconds
Started	Jun 04 02:39:21 PM PDT 24
Finished	Jun 04 02:43:36 PM PDT 24
Peak memory	245672 kb
Host	smart-9fcf39d1-447f-4432-9842-8119b5c61804
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584201244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.3584201244 +enable_masking=1 + sw_key_masked=0
Directory	/workspace/49.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/49.kmac_error.379634491
Short name	T839
Test name
Test status
Simulation time	24661254987 ps
CPU time	224.75 seconds
Started	Jun 04 02:39:13 PM PDT 24
Finished	Jun 04 02:42:58 PM PDT 24
Peak memory	252128 kb
Host	smart-7d43bc51-1718-4bc2-9c8d-0403450fb79e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=379634491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.379634491 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_error/latest

Test location	/workspace/coverage/default/49.kmac_key_error.2154224974
Short name	T6
Test name
Test status
Simulation time	647962074 ps
CPU time	1.4 seconds
Started	Jun 04 02:39:11 PM PDT 24
Finished	Jun 04 02:39:13 PM PDT 24
Peak memory	222592 kb
Host	smart-8867e13e-fcc7-4463-a860-bf3d5bf733d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2154224974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.2154224974 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_key_error/latest

Test location	/workspace/coverage/default/49.kmac_lc_escalation.1001635769
Short name	T44
Test name
Test status
Simulation time	60994813 ps
CPU time	1.36 seconds
Started	Jun 04 02:39:19 PM PDT 24
Finished	Jun 04 02:39:21 PM PDT 24
Peak memory	227304 kb
Host	smart-c5ded1fe-dbd5-45ea-94c7-4e4ef4380585
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1001635769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.1001635769 +enable_masking=1 +sw_k ey_masked=0
Directory	/workspace/49.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/49.kmac_long_msg_and_output.1817377568
Short name	T862
Test name
Test status
Simulation time	164454415466 ps
CPU time	2999.74 seconds
Started	Jun 04 02:38:50 PM PDT 24
Finished	Jun 04 03:28:51 PM PDT 24
Peak memory	450860 kb
Host	smart-415c7170-6aff-4b00-841c-4257b0b8d39b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817377568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a nd_output.1817377568 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/49.kmac_sideload.515131265
Short name	T967
Test name
Test status
Simulation time	52990707762 ps
CPU time	450.74 seconds
Started	Jun 04 02:38:50 PM PDT 24
Finished	Jun 04 02:46:22 PM PDT 24
Peak memory	254464 kb
Host	smart-a86bf34a-9b08-435d-a74e-f60b38358c52
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515131265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.515131265 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_sideload/latest

Test location	/workspace/coverage/default/49.kmac_smoke.1457061926
Short name	T327
Test name
Test status
Simulation time	1369551694 ps
CPU time	26.95 seconds
Started	Jun 04 02:38:50 PM PDT 24
Finished	Jun 04 02:39:18 PM PDT 24
Peak memory	227140 kb
Host	smart-83c3f364-cdbb-438b-b39b-49e361c877b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1457061926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1457061926 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_smoke/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_kmac.268997495
Short name	T492
Test name
Test status
Simulation time	898676634 ps
CPU time	6.59 seconds
Started	Jun 04 02:39:05 PM PDT 24
Finished	Jun 04 02:39:12 PM PDT 24
Peak memory	219360 kb
Host	smart-8a5e74d8-4da7-4ec9-9cee-82be3c75d8b9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268997495 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 49.kmac_test_vectors_kmac.268997495 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_kmac_xof.3594563817
Short name	T649
Test name
Test status
Simulation time	1524604781 ps
CPU time	6.47 seconds
Started	Jun 04 02:39:05 PM PDT 24
Finished	Jun 04 02:39:11 PM PDT 24
Peak memory	219216 kb
Host	smart-b5014d24-e078-4662-8a29-42bc80ad320a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594563817 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_kmac_xof.3594563817 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_224.447931771
Short name	T195
Test name
Test status
Simulation time	287565234432 ps
CPU time	2246.32 seconds
Started	Jun 04 02:38:58 PM PDT 24
Finished	Jun 04 03:16:25 PM PDT 24
Peak memory	401416 kb
Host	smart-56e921af-00fd-47fb-846b-2880b499d909
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=447931771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.447931771 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_256.1115061038
Short name	T204
Test name
Test status
Simulation time	19493492791 ps
CPU time	1806.44 seconds
Started	Jun 04 02:38:59 PM PDT 24
Finished	Jun 04 03:09:06 PM PDT 24
Peak memory	389768 kb
Host	smart-537c510e-35ec-44ab-b0a9-21b91294dd4e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1115061038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.1115061038 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_384.1594883148
Short name	T778
Test name
Test status
Simulation time	79257452802 ps
CPU time	1463.39 seconds
Started	Jun 04 02:38:59 PM PDT 24
Finished	Jun 04 03:03:23 PM PDT 24
Peak memory	339912 kb
Host	smart-a030e1f8-bb89-4311-9409-a2dd69c69602
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1594883148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.1594883148 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_512.1827059382
Short name	T1003
Test name
Test status
Simulation time	139483586645 ps
CPU time	1167.94 seconds
Started	Jun 04 02:38:58 PM PDT 24
Finished	Jun 04 02:58:27 PM PDT 24
Peak memory	301336 kb
Host	smart-bf5df27c-9b68-44c5-97aa-b002b2ab8e07
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1827059382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.1827059382 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_shake_128.1448864060
Short name	T500
Test name
Test status
Simulation time	267313310036 ps
CPU time	6207.29 seconds
Started	Jun 04 02:38:58 PM PDT 24
Finished	Jun 04 04:22:26 PM PDT 24
Peak memory	646756 kb
Host	smart-2093be1f-b8a3-4272-81a7-e0a8e4c64383
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1448864060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.1448864060 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_shake_256.855823549
Short name	T443
Test name
Test status
Simulation time	150036587407 ps
CPU time	4566.01 seconds
Started	Jun 04 02:38:58 PM PDT 24
Finished	Jun 04 03:55:05 PM PDT 24
Peak memory	573572 kb
Host	smart-696a7442-e080-4fde-8bd7-acde9d1f1ef2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=855823549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.855823549 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/5.kmac_alert_test.3789457747
Short name	T226
Test name
Test status
Simulation time	29237654 ps
CPU time	0.73 seconds
Started	Jun 04 02:24:00 PM PDT 24
Finished	Jun 04 02:24:01 PM PDT 24
Peak memory	218924 kb
Host	smart-88ea4f86-30ec-4ef2-8678-c96a236c181d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789457747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3789457747 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_alert_test/latest

Test location	/workspace/coverage/default/5.kmac_app.4049879253
Short name	T821
Test name
Test status
Simulation time	2269578109 ps
CPU time	127.2 seconds
Started	Jun 04 02:23:59 PM PDT 24
Finished	Jun 04 02:26:07 PM PDT 24
Peak memory	235824 kb
Host	smart-dd09d16a-5ec6-45e1-88aa-9c5087fbb213
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4049879253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.4049879253 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_app/latest

Test location	/workspace/coverage/default/5.kmac_app_with_partial_data.1446119036
Short name	T1024
Test name
Test status
Simulation time	5580003797 ps
CPU time	143.27 seconds
Started	Jun 04 02:23:57 PM PDT 24
Finished	Jun 04 02:26:21 PM PDT 24
Peak memory	237736 kb
Host	smart-1c270d1a-d61a-4d63-8e8c-2313cde03940
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1446119036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.1446119036 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/5.kmac_burst_write.1437558227
Short name	T396
Test name
Test status
Simulation time	4654018175 ps
CPU time	123.88 seconds
Started	Jun 04 02:23:59 PM PDT 24
Finished	Jun 04 02:26:04 PM PDT 24
Peak memory	226440 kb
Host	smart-ab9021f6-b1e1-4e98-842a-2af3b8ca54ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1437558227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.1437558227 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_burst_write/latest

Test location	/workspace/coverage/default/5.kmac_edn_timeout_error.2284998175
Short name	T1047
Test name
Test status
Simulation time	24354166 ps
CPU time	1.17 seconds
Started	Jun 04 02:24:00 PM PDT 24
Finished	Jun 04 02:24:02 PM PDT 24
Peak memory	223768 kb
Host	smart-5ed524d9-c918-4141-b520-768f2edd07ff
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2284998175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.2284998175 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_mode_error.1488922461
Short name	T776
Test name
Test status
Simulation time	21149971 ps
CPU time	0.89 seconds
Started	Jun 04 02:23:57 PM PDT 24
Finished	Jun 04 02:23:59 PM PDT 24
Peak memory	221080 kb
Host	smart-6651b597-54a9-46b4-b5cb-46eebc7cce9f
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1488922461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1488922461 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_refresh.1720086484
Short name	T861
Test name
Test status
Simulation time	12786142806 ps
CPU time	112.44 seconds
Started	Jun 04 02:23:56 PM PDT 24
Finished	Jun 04 02:25:49 PM PDT 24
Peak memory	235852 kb
Host	smart-28ec11c9-f1be-462e-b7d6-f962c37ef6a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1720086484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.1720086484 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/5.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/5.kmac_error.2759956660
Short name	T514
Test name
Test status
Simulation time	19975580303 ps
CPU time	407.36 seconds
Started	Jun 04 02:23:54 PM PDT 24
Finished	Jun 04 02:30:43 PM PDT 24
Peak memory	260192 kb
Host	smart-363c617c-d99c-43a8-bff7-41b92d981efc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2759956660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.2759956660 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_error/latest

Test location	/workspace/coverage/default/5.kmac_key_error.1134617234
Short name	T5
Test name
Test status
Simulation time	891271151 ps
CPU time	3.66 seconds
Started	Jun 04 02:23:55 PM PDT 24
Finished	Jun 04 02:23:59 PM PDT 24
Peak memory	223116 kb
Host	smart-ddcd3f7f-91d8-48a7-8888-b3b2f53d52aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1134617234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1134617234 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_key_error/latest

Test location	/workspace/coverage/default/5.kmac_lc_escalation.1146034850
Short name	T541
Test name
Test status
Simulation time	28657391 ps
CPU time	1.4 seconds
Started	Jun 04 02:23:58 PM PDT 24
Finished	Jun 04 02:24:00 PM PDT 24
Peak memory	227312 kb
Host	smart-ae9d7f2a-ac21-4160-9506-30def90200a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1146034850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.1146034850 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/5.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/5.kmac_long_msg_and_output.3696911698
Short name	T527
Test name
Test status
Simulation time	11709488309 ps
CPU time	615.24 seconds
Started	Jun 04 02:23:51 PM PDT 24
Finished	Jun 04 02:34:07 PM PDT 24
Peak memory	277616 kb
Host	smart-3af2d3b2-74a1-4826-8e0d-b072350dc79b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696911698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an d_output.3696911698 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/5.kmac_mubi.804869329
Short name	T1028
Test name
Test status
Simulation time	3891847972 ps
CPU time	108.85 seconds
Started	Jun 04 02:23:59 PM PDT 24
Finished	Jun 04 02:25:49 PM PDT 24
Peak memory	234708 kb
Host	smart-a6b283f7-6179-4011-abf4-4e1c6fd20fa6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=804869329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.804869329 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_mubi/latest

Test location	/workspace/coverage/default/5.kmac_sideload.3999004984
Short name	T983
Test name
Test status
Simulation time	585627112 ps
CPU time	8.4 seconds
Started	Jun 04 02:23:58 PM PDT 24
Finished	Jun 04 02:24:08 PM PDT 24
Peak memory	227396 kb
Host	smart-4449dcc6-7837-449a-8336-e55746f12434
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999004984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3999004984 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_sideload/latest

Test location	/workspace/coverage/default/5.kmac_smoke.2545828974
Short name	T798
Test name
Test status
Simulation time	2433487706 ps
CPU time	53.51 seconds
Started	Jun 04 02:23:55 PM PDT 24
Finished	Jun 04 02:24:49 PM PDT 24
Peak memory	227492 kb
Host	smart-24807211-99b8-421b-8c44-90a4757c65cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2545828974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.2545828974 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_smoke/latest

Test location	/workspace/coverage/default/5.kmac_stress_all.4004119411
Short name	T168
Test name
Test status
Simulation time	22682071131 ps
CPU time	1720.61 seconds
Started	Jun 04 02:23:55 PM PDT 24
Finished	Jun 04 02:52:37 PM PDT 24
Peak memory	421992 kb
Host	smart-1c113d70-bfd3-4728-afd6-821769e517ca
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4004119411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.4004119411 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_stress_all/latest

Test location	/workspace/coverage/default/5.kmac_stress_all_with_rand_reset.1567339467
Short name	T132
Test name
Test status
Simulation time	62196241968 ps
CPU time	706.21 seconds
Started	Jun 04 02:23:55 PM PDT 24
Finished	Jun 04 02:35:43 PM PDT 24
Peak memory	272624 kb
Host	smart-0128ca90-ad7c-47b4-ba27-bfa961050906
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1567339467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_rand_reset.1567339467 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_kmac.242294638
Short name	T667
Test name
Test status
Simulation time	332884699 ps
CPU time	6.45 seconds
Started	Jun 04 02:23:58 PM PDT 24
Finished	Jun 04 02:24:06 PM PDT 24
Peak memory	219272 kb
Host	smart-5ac3a9d9-7317-4d4a-b890-93d03bf80779
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242294638 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 5.kmac_test_vectors_kmac.242294638 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_kmac_xof.2186636970
Short name	T608
Test name
Test status
Simulation time	176499019 ps
CPU time	6.18 seconds
Started	Jun 04 02:23:57 PM PDT 24
Finished	Jun 04 02:24:04 PM PDT 24
Peak memory	219324 kb
Host	smart-81efd694-f828-4df7-933e-c12a550b5923
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186636970 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_kmac_xof.2186636970 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_224.479532737
Short name	T992
Test name
Test status
Simulation time	98685491683 ps
CPU time	2303.47 seconds
Started	Jun 04 02:23:57 PM PDT 24
Finished	Jun 04 03:02:22 PM PDT 24
Peak memory	388812 kb
Host	smart-1c028a80-2a5c-4040-8d21-0d165720d73a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=479532737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.479532737 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_256.2482670845
Short name	T349
Test name
Test status
Simulation time	607607845962 ps
CPU time	2052.97 seconds
Started	Jun 04 02:23:57 PM PDT 24
Finished	Jun 04 02:58:11 PM PDT 24
Peak memory	385820 kb
Host	smart-82ac1e76-bbae-405e-8d64-313921096399
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2482670845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.2482670845 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_384.3973031684
Short name	T303
Test name
Test status
Simulation time	16264368425 ps
CPU time	1560.43 seconds
Started	Jun 04 02:23:57 PM PDT 24
Finished	Jun 04 02:49:58 PM PDT 24
Peak memory	337592 kb
Host	smart-bc4b94c8-0431-4ad8-9e5c-b45a853c0d7b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3973031684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.3973031684 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_512.2544422339
Short name	T969
Test name
Test status
Simulation time	223234138485 ps
CPU time	1143.31 seconds
Started	Jun 04 02:24:00 PM PDT 24
Finished	Jun 04 02:43:04 PM PDT 24
Peak memory	301244 kb
Host	smart-36c11067-0dd7-4e5c-bba2-e2526293b53a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2544422339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.2544422339 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_shake_128.1847363946
Short name	T723
Test name
Test status
Simulation time	235552558321 ps
CPU time	5934.78 seconds
Started	Jun 04 02:23:58 PM PDT 24
Finished	Jun 04 04:02:54 PM PDT 24
Peak memory	654648 kb
Host	smart-072a8892-3efd-4569-bb22-7cc596a31758
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1847363946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.1847363946 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_shake_256.290704965
Short name	T694
Test name
Test status
Simulation time	218267392367 ps
CPU time	4498.99 seconds
Started	Jun 04 02:23:57 PM PDT 24
Finished	Jun 04 03:38:57 PM PDT 24
Peak memory	574816 kb
Host	smart-d3e2c350-0af7-4794-9ee8-a3efefbdbe78
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=290704965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.290704965 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/6.kmac_alert_test.3435634317
Short name	T115
Test name
Test status
Simulation time	23258702 ps
CPU time	0.85 seconds
Started	Jun 04 02:24:12 PM PDT 24
Finished	Jun 04 02:24:13 PM PDT 24
Peak memory	219068 kb
Host	smart-740d66e0-895a-4d1f-9d71-03597ad1f40f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435634317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.3435634317 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_alert_test/latest

Test location	/workspace/coverage/default/6.kmac_app.4155270929
Short name	T556
Test name
Test status
Simulation time	1073717842 ps
CPU time	52.95 seconds
Started	Jun 04 02:24:04 PM PDT 24
Finished	Jun 04 02:24:57 PM PDT 24
Peak memory	227788 kb
Host	smart-64ed1193-84bd-437f-9139-5f1ba7290bfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4155270929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.4155270929 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_app/latest

Test location	/workspace/coverage/default/6.kmac_app_with_partial_data.502605895
Short name	T625
Test name
Test status
Simulation time	13867852871 ps
CPU time	370.12 seconds
Started	Jun 04 02:24:03 PM PDT 24
Finished	Jun 04 02:30:13 PM PDT 24
Peak memory	254692 kb
Host	smart-fdb6840d-0062-479c-8e57-16f102f12034
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=502605895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.502605895 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/6.kmac_burst_write.4213399950
Short name	T684
Test name
Test status
Simulation time	67334036413 ps
CPU time	1135.56 seconds
Started	Jun 04 02:23:55 PM PDT 24
Finished	Jun 04 02:42:52 PM PDT 24
Peak memory	238044 kb
Host	smart-3c53c5de-2494-459d-b0f1-f0bab9665576
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4213399950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.4213399950 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_burst_write/latest

Test location	/workspace/coverage/default/6.kmac_edn_timeout_error.1396359150
Short name	T659
Test name
Test status
Simulation time	14067591 ps
CPU time	0.93 seconds
Started	Jun 04 02:24:08 PM PDT 24
Finished	Jun 04 02:24:09 PM PDT 24
Peak memory	222076 kb
Host	smart-6e20ad0c-8819-49d2-a2c1-e732f5bad037
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1396359150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.1396359150 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_mode_error.3833352135
Short name	T1022
Test name
Test status
Simulation time	22953242 ps
CPU time	1.03 seconds
Started	Jun 04 02:24:05 PM PDT 24
Finished	Jun 04 02:24:06 PM PDT 24
Peak memory	222152 kb
Host	smart-e45cb0b8-f5ff-44a7-bf8b-d8454c12a368
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3833352135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.3833352135 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_ready_error.2588590665
Short name	T11
Test name
Test status
Simulation time	1952513984 ps
CPU time	21.18 seconds
Started	Jun 04 02:24:06 PM PDT 24
Finished	Jun 04 02:24:28 PM PDT 24
Peak memory	227380 kb
Host	smart-3e15ec4f-d405-4032-810e-e0654e9ec533
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2588590665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.2588590665 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/6.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_refresh.1669519346
Short name	T736
Test name
Test status
Simulation time	20151649269 ps
CPU time	120.15 seconds
Started	Jun 04 02:24:05 PM PDT 24
Finished	Jun 04 02:26:05 PM PDT 24
Peak memory	235136 kb
Host	smart-ff5572fd-8228-4ab8-b72d-5aa2c1b5d7a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1669519346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.1669519346 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/6.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/6.kmac_error.1357896885
Short name	T700
Test name
Test status
Simulation time	8963722253 ps
CPU time	97.34 seconds
Started	Jun 04 02:24:02 PM PDT 24
Finished	Jun 04 02:25:40 PM PDT 24
Peak memory	243836 kb
Host	smart-12ca6065-f07f-4691-912b-61522862781b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1357896885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.1357896885 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_error/latest

Test location	/workspace/coverage/default/6.kmac_key_error.3947003856
Short name	T1043
Test name
Test status
Simulation time	6062533234 ps
CPU time	7.4 seconds
Started	Jun 04 02:24:04 PM PDT 24
Finished	Jun 04 02:24:12 PM PDT 24
Peak memory	224720 kb
Host	smart-1587a386-3073-48dc-9cef-977f2914aaf8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3947003856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.3947003856 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_key_error/latest

Test location	/workspace/coverage/default/6.kmac_lc_escalation.4206580967
Short name	T429
Test name
Test status
Simulation time	51239194 ps
CPU time	1.46 seconds
Started	Jun 04 02:24:01 PM PDT 24
Finished	Jun 04 02:24:03 PM PDT 24
Peak memory	227328 kb
Host	smart-b2b1c952-fe07-4a22-865b-2acfb68ac533
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4206580967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.4206580967 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/6.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/6.kmac_long_msg_and_output.3529282405
Short name	T816
Test name
Test status
Simulation time	84937632831 ps
CPU time	3118.01 seconds
Started	Jun 04 02:23:59 PM PDT 24
Finished	Jun 04 03:15:58 PM PDT 24
Peak memory	455912 kb
Host	smart-eac986df-698c-4ecc-9b50-a036d867a387
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529282405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an d_output.3529282405 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/6.kmac_mubi.4183194933
Short name	T423
Test name
Test status
Simulation time	62686252452 ps
CPU time	389.91 seconds
Started	Jun 04 02:24:04 PM PDT 24
Finished	Jun 04 02:30:35 PM PDT 24
Peak memory	256388 kb
Host	smart-14987223-fd5c-4649-9ae8-736a7b23669d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4183194933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.4183194933 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_mubi/latest

Test location	/workspace/coverage/default/6.kmac_sideload.3298843869
Short name	T280
Test name
Test status
Simulation time	28670101614 ps
CPU time	208.17 seconds
Started	Jun 04 02:24:00 PM PDT 24
Finished	Jun 04 02:27:29 PM PDT 24
Peak memory	242796 kb
Host	smart-fb5001a1-a171-4db5-8642-f05cdd42d51e
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298843869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.3298843869 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_sideload/latest

Test location	/workspace/coverage/default/6.kmac_smoke.1382224959
Short name	T294
Test name
Test status
Simulation time	657343743 ps
CPU time	7.69 seconds
Started	Jun 04 02:23:56 PM PDT 24
Finished	Jun 04 02:24:05 PM PDT 24
Peak memory	224012 kb
Host	smart-03dd0fd2-a78f-4c93-8515-ff892903d005
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1382224959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.1382224959 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_smoke/latest

Test location	/workspace/coverage/default/6.kmac_stress_all.2155207037
Short name	T56
Test name
Test status
Simulation time	41385059460 ps
CPU time	1013.9 seconds
Started	Jun 04 02:24:05 PM PDT 24
Finished	Jun 04 02:41:00 PM PDT 24
Peak memory	348680 kb
Host	smart-8d6a204a-6c4b-43ba-b543-c322160bdda3
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2155207037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.2155207037 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_stress_all/latest

Test location	/workspace/coverage/default/6.kmac_stress_all_with_rand_reset.351766666
Short name	T79
Test name
Test status
Simulation time	123251219786 ps
CPU time	1367.73 seconds
Started	Jun 04 02:24:09 PM PDT 24
Finished	Jun 04 02:46:57 PM PDT 24
Peak memory	285228 kb
Host	smart-7d3450e3-e033-4fd4-8314-6e67a4801836
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=351766666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_rand_reset.351766666 +enab le_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_kmac.1736306276
Short name	T598
Test name
Test status
Simulation time	633006724 ps
CPU time	6.23 seconds
Started	Jun 04 02:24:04 PM PDT 24
Finished	Jun 04 02:24:10 PM PDT 24
Peak memory	220280 kb
Host	smart-0337aa0e-7bad-437b-83d0-2cdf8ecc4ccf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736306276 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.kmac_test_vectors_kmac.1736306276 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_kmac_xof.1315773259
Short name	T320
Test name
Test status
Simulation time	458881499 ps
CPU time	5.31 seconds
Started	Jun 04 02:24:04 PM PDT 24
Finished	Jun 04 02:24:10 PM PDT 24
Peak memory	219340 kb
Host	smart-4d13defc-ac4e-45ca-be14-cad8d7803543
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315773259 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_kmac_xof.1315773259 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_224.2495620782
Short name	T748
Test name
Test status
Simulation time	261182227745 ps
CPU time	2242.1 seconds
Started	Jun 04 02:23:56 PM PDT 24
Finished	Jun 04 03:01:19 PM PDT 24
Peak memory	396840 kb
Host	smart-f20000fb-483e-444f-a870-1e5674e2809a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2495620782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.2495620782 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_256.436984808
Short name	T380
Test name
Test status
Simulation time	64365165655 ps
CPU time	2174.93 seconds
Started	Jun 04 02:23:59 PM PDT 24
Finished	Jun 04 03:00:15 PM PDT 24
Peak memory	390188 kb
Host	smart-987b85ad-0912-41c1-b47f-59ace2973e36
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=436984808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.436984808 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_384.3653726857
Short name	T199
Test name
Test status
Simulation time	60168737978 ps
CPU time	1478.67 seconds
Started	Jun 04 02:23:57 PM PDT 24
Finished	Jun 04 02:48:36 PM PDT 24
Peak memory	339252 kb
Host	smart-67b47c4d-298c-4136-9a5c-b98d55647da7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3653726857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.3653726857 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_512.2153950349
Short name	T1081
Test name
Test status
Simulation time	41601404594 ps
CPU time	1098.48 seconds
Started	Jun 04 02:23:58 PM PDT 24
Finished	Jun 04 02:42:17 PM PDT 24
Peak memory	299768 kb
Host	smart-c115bcbf-567e-40e2-9f03-856668e5e214
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2153950349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.2153950349 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_shake_128.2191866715
Short name	T958
Test name
Test status
Simulation time	263368857943 ps
CPU time	6307.48 seconds
Started	Jun 04 02:24:04 PM PDT 24
Finished	Jun 04 04:09:13 PM PDT 24
Peak memory	635428 kb
Host	smart-4114d0e5-0780-442d-b57c-7eef0008af85
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2191866715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.2191866715 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_shake_256.3552508322
Short name	T544
Test name
Test status
Simulation time	60025198715 ps
CPU time	4418.24 seconds
Started	Jun 04 02:24:02 PM PDT 24
Finished	Jun 04 03:37:42 PM PDT 24
Peak memory	556840 kb
Host	smart-57551417-51ed-422c-aa09-a62b2bbdd2c8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3552508322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.3552508322 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/7.kmac_alert_test.767184529
Short name	T838
Test name
Test status
Simulation time	48109601 ps
CPU time	0.84 seconds
Started	Jun 04 02:24:16 PM PDT 24
Finished	Jun 04 02:24:17 PM PDT 24
Peak memory	218936 kb
Host	smart-0067bc96-a918-4dc8-ad25-2d3a3d9e9ad1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767184529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.767184529 +enable_ma sking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_alert_test/latest

Test location	/workspace/coverage/default/7.kmac_app.3832699427
Short name	T724
Test name
Test status
Simulation time	13979842495 ps
CPU time	344.79 seconds
Started	Jun 04 02:24:10 PM PDT 24
Finished	Jun 04 02:29:55 PM PDT 24
Peak memory	247532 kb
Host	smart-0f8433ed-f386-4c4b-bbf8-5aaac410badb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3832699427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.3832699427 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_app/latest

Test location	/workspace/coverage/default/7.kmac_app_with_partial_data.2667586363
Short name	T323
Test name
Test status
Simulation time	2778505722 ps
CPU time	37.43 seconds
Started	Jun 04 02:24:10 PM PDT 24
Finished	Jun 04 02:24:48 PM PDT 24
Peak memory	227812 kb
Host	smart-0b04ba53-b501-460f-a62c-a6280bb4d3a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2667586363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.2667586363 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/7.kmac_burst_write.2712879313
Short name	T901
Test name
Test status
Simulation time	29724294742 ps
CPU time	834.06 seconds
Started	Jun 04 02:24:10 PM PDT 24
Finished	Jun 04 02:38:04 PM PDT 24
Peak memory	236052 kb
Host	smart-752ce7be-256a-4cd4-8252-2238b7279cd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2712879313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.2712879313 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_burst_write/latest

Test location	/workspace/coverage/default/7.kmac_edn_timeout_error.2188588172
Short name	T528
Test name
Test status
Simulation time	36440860 ps
CPU time	0.82 seconds
Started	Jun 04 02:24:17 PM PDT 24
Finished	Jun 04 02:24:18 PM PDT 24
Peak memory	221960 kb
Host	smart-bfadffa7-1517-4920-b49c-e3eb4fa5dc7e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2188588172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.2188588172 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_mode_error.3775100249
Short name	T639
Test name
Test status
Simulation time	41038751 ps
CPU time	1.39 seconds
Started	Jun 04 02:24:15 PM PDT 24
Finished	Jun 04 02:24:17 PM PDT 24
Peak memory	223016 kb
Host	smart-dbd1ba2f-7f73-44c1-bad0-dfb349bd0541
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3775100249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.3775100249 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_ready_error.774695447
Short name	T9
Test name
Test status
Simulation time	4298114242 ps
CPU time	47.82 seconds
Started	Jun 04 02:24:16 PM PDT 24
Finished	Jun 04 02:25:05 PM PDT 24
Peak memory	227432 kb
Host	smart-36a653c1-462c-4b9c-84d3-01764a00b43b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=774695447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.774695447 +enable_maskin g=1 +sw_key_masked=0
Directory	/workspace/7.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_refresh.1425072717
Short name	T231
Test name
Test status
Simulation time	8681806223 ps
CPU time	187.7 seconds
Started	Jun 04 02:24:10 PM PDT 24
Finished	Jun 04 02:27:18 PM PDT 24
Peak memory	239544 kb
Host	smart-ece61057-a1b2-432d-a55c-bc1dfa7f0935
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1425072717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.1425072717 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/7.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/7.kmac_error.1391701624
Short name	T711
Test name
Test status
Simulation time	2081049700 ps
CPU time	54.52 seconds
Started	Jun 04 02:24:08 PM PDT 24
Finished	Jun 04 02:25:03 PM PDT 24
Peak memory	238436 kb
Host	smart-5e89d778-8790-4c2d-afe8-cbfd9f405a24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1391701624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.1391701624 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_error/latest

Test location	/workspace/coverage/default/7.kmac_key_error.3688660216
Short name	T758
Test name
Test status
Simulation time	17421287064 ps
CPU time	13.59 seconds
Started	Jun 04 02:24:09 PM PDT 24
Finished	Jun 04 02:24:24 PM PDT 24
Peak memory	225956 kb
Host	smart-bc5f8c31-38d9-4e7f-8220-ac89929c45cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3688660216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.3688660216 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_key_error/latest

Test location	/workspace/coverage/default/7.kmac_lc_escalation.3143739929
Short name	T837
Test name
Test status
Simulation time	1009668474 ps
CPU time	25.17 seconds
Started	Jun 04 02:24:16 PM PDT 24
Finished	Jun 04 02:24:42 PM PDT 24
Peak memory	235648 kb
Host	smart-448ba384-c137-471f-93e2-aaa2a40d9863
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143739929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.3143739929 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/7.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/7.kmac_long_msg_and_output.3960133961
Short name	T504
Test name
Test status
Simulation time	19505817991 ps
CPU time	1873.88 seconds
Started	Jun 04 02:24:08 PM PDT 24
Finished	Jun 04 02:55:23 PM PDT 24
Peak memory	401384 kb
Host	smart-1e6fadc9-8b84-46e1-8566-b2823bd74f67
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960133961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an d_output.3960133961 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/7.kmac_mubi.488526796
Short name	T1027
Test name
Test status
Simulation time	45329059986 ps
CPU time	385.64 seconds
Started	Jun 04 02:24:07 PM PDT 24
Finished	Jun 04 02:30:34 PM PDT 24
Peak memory	255824 kb
Host	smart-226c9f2d-23c8-4226-8b87-8bd9705e2c5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=488526796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.488526796 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_mubi/latest

Test location	/workspace/coverage/default/7.kmac_sideload.2291909060
Short name	T745
Test name
Test status
Simulation time	56414232417 ps
CPU time	422.65 seconds
Started	Jun 04 02:24:10 PM PDT 24
Finished	Jun 04 02:31:14 PM PDT 24
Peak memory	252344 kb
Host	smart-5c55cbf6-c128-4cac-83df-1963fa00dae8
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291909060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.2291909060 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_sideload/latest

Test location	/workspace/coverage/default/7.kmac_smoke.2562059421
Short name	T431
Test name
Test status
Simulation time	18016238640 ps
CPU time	85.31 seconds
Started	Jun 04 02:24:08 PM PDT 24
Finished	Jun 04 02:25:34 PM PDT 24
Peak memory	227468 kb
Host	smart-42f0aa33-d087-4fbe-bb2a-991412aab86d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2562059421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.2562059421 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_smoke/latest

Test location	/workspace/coverage/default/7.kmac_stress_all.32636081
Short name	T505
Test name
Test status
Simulation time	49425851435 ps
CPU time	1892.36 seconds
Started	Jun 04 02:24:17 PM PDT 24
Finished	Jun 04 02:55:50 PM PDT 24
Peak memory	391652 kb
Host	smart-4a2c666f-dc54-42df-9e96-67ce861e669a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=32636081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.32636081 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_stress_all/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_kmac.3218525991
Short name	T566
Test name
Test status
Simulation time	128384222 ps
CPU time	5.76 seconds
Started	Jun 04 02:24:09 PM PDT 24
Finished	Jun 04 02:24:16 PM PDT 24
Peak memory	219292 kb
Host	smart-790605d3-31c2-4cc2-8d60-08601655a8f0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218525991 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.kmac_test_vectors_kmac.3218525991 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_kmac_xof.3309838473
Short name	T314
Test name
Test status
Simulation time	511977679 ps
CPU time	6.25 seconds
Started	Jun 04 02:24:09 PM PDT 24
Finished	Jun 04 02:24:16 PM PDT 24
Peak memory	219328 kb
Host	smart-242d735d-5518-4c98-bc99-801b2dacd51c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309838473 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_kmac_xof.3309838473 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_224.967312418
Short name	T1019
Test name
Test status
Simulation time	192391041350 ps
CPU time	2424.1 seconds
Started	Jun 04 02:24:08 PM PDT 24
Finished	Jun 04 03:04:33 PM PDT 24
Peak memory	394640 kb
Host	smart-cb5cb0d4-a7de-4de7-8862-2cc7b610a2f8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=967312418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.967312418 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_256.1149262075
Short name	T350
Test name
Test status
Simulation time	96557028762 ps
CPU time	2234.84 seconds
Started	Jun 04 02:24:10 PM PDT 24
Finished	Jun 04 03:01:25 PM PDT 24
Peak memory	389564 kb
Host	smart-1a1a926d-7abf-46bf-b312-1496dbfe4f88
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1149262075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.1149262075 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_384.543985084
Short name	T678
Test name
Test status
Simulation time	190892714061 ps
CPU time	1788.76 seconds
Started	Jun 04 02:24:09 PM PDT 24
Finished	Jun 04 02:53:59 PM PDT 24
Peak memory	341664 kb
Host	smart-36d08bb1-453d-41f5-8192-b5f1dbcc50d5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=543985084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.543985084 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_512.1766553539
Short name	T464
Test name
Test status
Simulation time	46819398342 ps
CPU time	1236.83 seconds
Started	Jun 04 02:24:07 PM PDT 24
Finished	Jun 04 02:44:45 PM PDT 24
Peak memory	302516 kb
Host	smart-d35d5e9a-2ec1-411a-9b04-b10d49c36d9f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1766553539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.1766553539 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_shake_128.4276190872
Short name	T873
Test name
Test status
Simulation time	242756711958 ps
CPU time	5290.22 seconds
Started	Jun 04 02:24:09 PM PDT 24
Finished	Jun 04 03:52:21 PM PDT 24
Peak memory	662580 kb
Host	smart-ff58f988-3715-4e6c-9efa-08f3df4ec040
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4276190872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.4276190872 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_shake_256.3159828003
Short name	T238
Test name
Test status
Simulation time	154529705652 ps
CPU time	5122.32 seconds
Started	Jun 04 02:24:08 PM PDT 24
Finished	Jun 04 03:49:32 PM PDT 24
Peak memory	568044 kb
Host	smart-74bbc14d-69b6-4380-8852-986016956a16
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3159828003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.3159828003 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/8.kmac_alert_test.1890170743
Short name	T353
Test name
Test status
Simulation time	17451714 ps
CPU time	0.84 seconds
Started	Jun 04 02:24:31 PM PDT 24
Finished	Jun 04 02:24:32 PM PDT 24
Peak memory	218944 kb
Host	smart-e99e03e5-5ad1-46bc-b4dc-3c986cbd08e3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890170743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.1890170743 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_alert_test/latest

Test location	/workspace/coverage/default/8.kmac_app.2880985907
Short name	T446
Test name
Test status
Simulation time	10010293377 ps
CPU time	223.79 seconds
Started	Jun 04 02:24:23 PM PDT 24
Finished	Jun 04 02:28:08 PM PDT 24
Peak memory	244844 kb
Host	smart-862c0fac-3d5c-494d-b335-f2fa827434f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2880985907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.2880985907 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_app/latest

Test location	/workspace/coverage/default/8.kmac_burst_write.1960840712
Short name	T467
Test name
Test status
Simulation time	8358805337 ps
CPU time	252.02 seconds
Started	Jun 04 02:24:15 PM PDT 24
Finished	Jun 04 02:28:28 PM PDT 24
Peak memory	230060 kb
Host	smart-b98e15d3-97cc-4d7c-8506-5506dc0138b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1960840712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.1960840712 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_burst_write/latest

Test location	/workspace/coverage/default/8.kmac_edn_timeout_error.1928484660
Short name	T66
Test name
Test status
Simulation time	23684318 ps
CPU time	1.08 seconds
Started	Jun 04 02:24:25 PM PDT 24
Finished	Jun 04 02:24:27 PM PDT 24
Peak memory	223544 kb
Host	smart-7c334f62-479e-430c-9772-fd9e7b3cad77
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1928484660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.1928484660 +enabl e_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_mode_error.1590099547
Short name	T812
Test name
Test status
Simulation time	31660954 ps
CPU time	1.07 seconds
Started	Jun 04 02:24:25 PM PDT 24
Finished	Jun 04 02:24:26 PM PDT 24
Peak memory	222260 kb
Host	smart-e356a8be-07f3-4cad-a11c-2eb56a77b0dd
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1590099547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.1590099547 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_ready_error.4181456115
Short name	T795
Test name
Test status
Simulation time	21762379468 ps
CPU time	52.6 seconds
Started	Jun 04 02:24:23 PM PDT 24
Finished	Jun 04 02:25:16 PM PDT 24
Peak memory	227464 kb
Host	smart-e7589046-9a0a-4105-a6b1-d3c756f70a89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4181456115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.4181456115 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/8.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_refresh.4269919134
Short name	T874
Test name
Test status
Simulation time	6556686896 ps
CPU time	203.78 seconds
Started	Jun 04 02:24:26 PM PDT 24
Finished	Jun 04 02:27:51 PM PDT 24
Peak memory	242300 kb
Host	smart-7f5ed151-5cb9-4190-a664-bc4f9a555bad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4269919134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.4269919134 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/8.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/8.kmac_error.2048960155
Short name	T808
Test name
Test status
Simulation time	1159832918 ps
CPU time	27.17 seconds
Started	Jun 04 02:24:23 PM PDT 24
Finished	Jun 04 02:24:51 PM PDT 24
Peak memory	243628 kb
Host	smart-aa031c7a-bd3e-44e5-9c3c-19bcf901722f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2048960155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.2048960155 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_error/latest

Test location	/workspace/coverage/default/8.kmac_key_error.1073539414
Short name	T452
Test name
Test status
Simulation time	5807245461 ps
CPU time	9.91 seconds
Started	Jun 04 02:24:24 PM PDT 24
Finished	Jun 04 02:24:34 PM PDT 24
Peak memory	226036 kb
Host	smart-ae4ce84d-edd6-4ebc-964d-8047ad90bd1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1073539414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.1073539414 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_key_error/latest

Test location	/workspace/coverage/default/8.kmac_lc_escalation.357518118
Short name	T30
Test name
Test status
Simulation time	2957033019 ps
CPU time	37.72 seconds
Started	Jun 04 02:24:26 PM PDT 24
Finished	Jun 04 02:25:04 PM PDT 24
Peak memory	238028 kb
Host	smart-5701aa87-920c-4f1b-a6a4-bf6b78fd63ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=357518118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.357518118 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/8.kmac_long_msg_and_output.286819063
Short name	T962
Test name
Test status
Simulation time	265462128888 ps
CPU time	1487.38 seconds
Started	Jun 04 02:24:17 PM PDT 24
Finished	Jun 04 02:49:05 PM PDT 24
Peak memory	350472 kb
Host	smart-19ac92b2-24c2-4781-b0a1-f2d474fc3b94
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286819063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and _output.286819063 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/8.kmac_mubi.689214318
Short name	T973
Test name
Test status
Simulation time	17442130453 ps
CPU time	106 seconds
Started	Jun 04 02:24:25 PM PDT 24
Finished	Jun 04 02:26:11 PM PDT 24
Peak memory	234600 kb
Host	smart-14ba6547-9342-4d18-a50d-e09b4231b7a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=689214318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.689214318 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_mubi/latest

Test location	/workspace/coverage/default/8.kmac_sideload.2722799133
Short name	T633
Test name
Test status
Simulation time	46289656621 ps
CPU time	204.05 seconds
Started	Jun 04 02:24:18 PM PDT 24
Finished	Jun 04 02:27:43 PM PDT 24
Peak memory	240800 kb
Host	smart-009512f9-1ed7-4c1a-9f95-3abfe0ceba13
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722799133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2722799133 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_sideload/latest

Test location	/workspace/coverage/default/8.kmac_smoke.2399824814
Short name	T153
Test name
Test status
Simulation time	4056512083 ps
CPU time	49.04 seconds
Started	Jun 04 02:24:16 PM PDT 24
Finished	Jun 04 02:25:06 PM PDT 24
Peak memory	223596 kb
Host	smart-2b423b53-b321-40f9-a6d2-6b480283acc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2399824814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.2399824814 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_smoke/latest

Test location	/workspace/coverage/default/8.kmac_stress_all.425049948
Short name	T622
Test name
Test status
Simulation time	25945941657 ps
CPU time	372.03 seconds
Started	Jun 04 02:24:23 PM PDT 24
Finished	Jun 04 02:30:35 PM PDT 24
Peak memory	279184 kb
Host	smart-420f02d7-7774-43d9-8a72-3d746517a14c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=425049948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.425049948 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_stress_all/latest

Test location	/workspace/coverage/default/8.kmac_stress_all_with_rand_reset.2132284379
Short name	T24
Test name
Test status
Simulation time	122564646991 ps
CPU time	294.51 seconds
Started	Jun 04 02:24:23 PM PDT 24
Finished	Jun 04 02:29:18 PM PDT 24
Peak memory	260376 kb
Host	smart-779760cf-7b65-4288-91ee-8fcd75eb8db6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2132284379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_with_rand_reset.2132284379 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_kmac.1563765269
Short name	T1082
Test name
Test status
Simulation time	202149876 ps
CPU time	5.43 seconds
Started	Jun 04 02:24:23 PM PDT 24
Finished	Jun 04 02:24:29 PM PDT 24
Peak memory	219348 kb
Host	smart-93f386da-6536-42e8-a4b3-1f98eb1b5922
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563765269 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.kmac_test_vectors_kmac.1563765269 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_kmac_xof.2666774322
Short name	T702
Test name
Test status
Simulation time	100657462 ps
CPU time	5.87 seconds
Started	Jun 04 02:24:23 PM PDT 24
Finished	Jun 04 02:24:30 PM PDT 24
Peak memory	219152 kb
Host	smart-923ae719-7d29-48ea-b36a-8e97ee479d34
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666774322 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_kmac_xof.2666774322 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_224.692246540
Short name	T520
Test name
Test status
Simulation time	20902021313 ps
CPU time	2022.87 seconds
Started	Jun 04 02:24:17 PM PDT 24
Finished	Jun 04 02:58:01 PM PDT 24
Peak memory	392732 kb
Host	smart-56ce59a8-d6fa-47e2-840f-9618f677e160
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=692246540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.692246540 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_256.597736958
Short name	T1001
Test name
Test status
Simulation time	321443876075 ps
CPU time	2157.52 seconds
Started	Jun 04 02:24:17 PM PDT 24
Finished	Jun 04 03:00:15 PM PDT 24
Peak memory	387796 kb
Host	smart-a4765c60-e8e1-4d91-9074-01eb7c8d2a92
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=597736958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.597736958 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_384.1543493788
Short name	T362
Test name
Test status
Simulation time	368641623066 ps
CPU time	1531.56 seconds
Started	Jun 04 02:24:14 PM PDT 24
Finished	Jun 04 02:49:47 PM PDT 24
Peak memory	338180 kb
Host	smart-e1a3fd25-e14e-44a0-ad21-ac41d495030b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1543493788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.1543493788 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_512.604869770
Short name	T867
Test name
Test status
Simulation time	13035984982 ps
CPU time	1351.95 seconds
Started	Jun 04 02:24:15 PM PDT 24
Finished	Jun 04 02:46:48 PM PDT 24
Peak memory	305500 kb
Host	smart-6896fa67-6ca3-4a8f-b5e9-b188358b7b96
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=604869770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.604869770 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_shake_128.448624672
Short name	T286
Test name
Test status
Simulation time	68754155510 ps
CPU time	5186.05 seconds
Started	Jun 04 02:24:24 PM PDT 24
Finished	Jun 04 03:50:52 PM PDT 24
Peak memory	645868 kb
Host	smart-25f4fc84-8206-46ad-b530-3c62f2f029fa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=448624672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.448624672 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_shake_256.458258210
Short name	T509
Test name
Test status
Simulation time	1070652982337 ps
CPU time	4398.78 seconds
Started	Jun 04 02:24:27 PM PDT 24
Finished	Jun 04 03:37:47 PM PDT 24
Peak memory	567308 kb
Host	smart-bd6e0870-1c46-49dd-8260-b707c559be3f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=458258210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.458258210 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/9.kmac_alert_test.4271185162
Short name	T114
Test name
Test status
Simulation time	18826119 ps
CPU time	0.85 seconds
Started	Jun 04 02:24:47 PM PDT 24
Finished	Jun 04 02:24:49 PM PDT 24
Peak memory	218912 kb
Host	smart-a276d0fa-012e-4ad9-8d5c-33598b40c338
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271185162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.4271185162 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_alert_test/latest

Test location	/workspace/coverage/default/9.kmac_app.2933482389
Short name	T934
Test name
Test status
Simulation time	40673356699 ps
CPU time	109.14 seconds
Started	Jun 04 02:24:36 PM PDT 24
Finished	Jun 04 02:26:26 PM PDT 24
Peak memory	235176 kb
Host	smart-110c0f21-a920-4726-9a1d-7abf50ee60d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2933482389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.2933482389 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_app/latest

Test location	/workspace/coverage/default/9.kmac_app_with_partial_data.2780944174
Short name	T998
Test name
Test status
Simulation time	57110502871 ps
CPU time	398.25 seconds
Started	Jun 04 02:24:36 PM PDT 24
Finished	Jun 04 02:31:15 PM PDT 24
Peak memory	252492 kb
Host	smart-d9f36be8-7e76-4597-9035-f2f60b7da75d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2780944174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.2780944174 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/9.kmac_edn_timeout_error.145058138
Short name	T817
Test name
Test status
Simulation time	183857133 ps
CPU time	6.42 seconds
Started	Jun 04 02:24:36 PM PDT 24
Finished	Jun 04 02:24:43 PM PDT 24
Peak memory	227232 kb
Host	smart-75d36056-c049-4dd0-b9de-a96df42d6344
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=145058138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.145058138 +enable_ masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_mode_error.1860360649
Short name	T570
Test name
Test status
Simulation time	78168695 ps
CPU time	1.25 seconds
Started	Jun 04 02:24:35 PM PDT 24
Finished	Jun 04 02:24:36 PM PDT 24
Peak memory	219024 kb
Host	smart-e83ce2a2-eca5-4b40-ac2e-398ded51ea1e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1860360649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.1860360649 +ena ble_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_ready_error.1283062368
Short name	T793
Test name
Test status
Simulation time	3746677051 ps
CPU time	48.47 seconds
Started	Jun 04 02:24:43 PM PDT 24
Finished	Jun 04 02:25:32 PM PDT 24
Peak memory	227500 kb
Host	smart-d55701b8-4ea3-42c1-a525-f346039ecd09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283062368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.1283062368 +enable_mask ing=1 +sw_key_masked=0
Directory	/workspace/9.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_refresh.3577250531
Short name	T482
Test name
Test status
Simulation time	4566341091 ps
CPU time	49.29 seconds
Started	Jun 04 02:24:35 PM PDT 24
Finished	Jun 04 02:25:25 PM PDT 24
Peak memory	235672 kb
Host	smart-04ba7466-a2e7-472b-8798-e63210548bc2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577250531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.3577250531 +enable_masking=1 +s w_key_masked=0
Directory	/workspace/9.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/9.kmac_error.3446837617
Short name	T697
Test name
Test status
Simulation time	55255386330 ps
CPU time	453.1 seconds
Started	Jun 04 02:24:35 PM PDT 24
Finished	Jun 04 02:32:09 PM PDT 24
Peak memory	260320 kb
Host	smart-e31e1d49-b7a1-49a7-9dd9-3f67117dd959
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3446837617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.3446837617 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_error/latest

Test location	/workspace/coverage/default/9.kmac_key_error.2984465470
Short name	T548
Test name
Test status
Simulation time	1639146423 ps
CPU time	11.23 seconds
Started	Jun 04 02:24:35 PM PDT 24
Finished	Jun 04 02:24:46 PM PDT 24
Peak memory	224788 kb
Host	smart-6d3d24de-7684-4917-9d0d-3ff26da6a2b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2984465470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.2984465470 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_key_error/latest

Test location	/workspace/coverage/default/9.kmac_lc_escalation.3317130568
Short name	T607
Test name
Test status
Simulation time	126275383 ps
CPU time	1.43 seconds
Started	Jun 04 02:24:42 PM PDT 24
Finished	Jun 04 02:24:45 PM PDT 24
Peak memory	227316 kb
Host	smart-66aa6e0d-6452-4c87-b634-bb7825320a11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3317130568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.3317130568 +enable_masking=1 +sw_ke y_masked=0
Directory	/workspace/9.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/9.kmac_long_msg_and_output.321959845
Short name	T298
Test name
Test status
Simulation time	48787533887 ps
CPU time	2314 seconds
Started	Jun 04 02:24:28 PM PDT 24
Finished	Jun 04 03:03:03 PM PDT 24
Peak memory	434396 kb
Host	smart-fe1837d9-37a9-4b9a-be6a-ddb57210490f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321959845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and _output.321959845 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/9.kmac_mubi.512064529
Short name	T1072
Test name
Test status
Simulation time	19366030385 ps
CPU time	456.89 seconds
Started	Jun 04 02:24:36 PM PDT 24
Finished	Jun 04 02:32:13 PM PDT 24
Peak memory	256940 kb
Host	smart-58fc4f00-52e9-4d68-9b68-6a7d1f01d7e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=512064529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.512064529 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_mubi/latest

Test location	/workspace/coverage/default/9.kmac_sideload.2577898367
Short name	T846
Test name
Test status
Simulation time	11605797456 ps
CPU time	354.03 seconds
Started	Jun 04 02:24:34 PM PDT 24
Finished	Jun 04 02:30:29 PM PDT 24
Peak memory	251140 kb
Host	smart-5788803c-3481-49b1-936f-7303dabc5103
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577898367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.2577898367 +en able_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_sideload/latest

Test location	/workspace/coverage/default/9.kmac_smoke.3550084808
Short name	T890
Test name
Test status
Simulation time	14852376569 ps
CPU time	64.64 seconds
Started	Jun 04 02:24:34 PM PDT 24
Finished	Jun 04 02:25:39 PM PDT 24
Peak memory	227448 kb
Host	smart-c2b2efc4-e05a-4f6e-a55b-65291a974e96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550084808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.3550084808 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_smoke/latest

Test location	/workspace/coverage/default/9.kmac_stress_all.107183321
Short name	T1083
Test name
Test status
Simulation time	16382183740 ps
CPU time	639.28 seconds
Started	Jun 04 02:24:43 PM PDT 24
Finished	Jun 04 02:35:23 PM PDT 24
Peak memory	258348 kb
Host	smart-03916c07-f92d-47db-9f2b-0f25360ddecb
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=107183321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.107183321 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_stress_all/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_kmac.36442173
Short name	T459
Test name
Test status
Simulation time	124487012 ps
CPU time	5.15 seconds
Started	Jun 04 02:24:37 PM PDT 24
Finished	Jun 04 02:24:43 PM PDT 24
Peak memory	219260 kb
Host	smart-405887c8-c49b-4a77-9edb-bebdb4404aac
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36442173 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 9.kmac_test_vectors_kmac.36442173 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_kmac_xof.469748309
Short name	T1021
Test name
Test status
Simulation time	200838486 ps
CPU time	5.73 seconds
Started	Jun 04 02:24:37 PM PDT 24
Finished	Jun 04 02:24:43 PM PDT 24
Peak memory	219248 kb
Host	smart-cd3c445b-3621-4fb3-bc36-f5d5916606c6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469748309 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 9.kmac_test_vectors_kmac_xof.469748309 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_224.3370284203
Short name	T260
Test name
Test status
Simulation time	868080185831 ps
CPU time	2240.18 seconds
Started	Jun 04 02:24:34 PM PDT 24
Finished	Jun 04 03:01:55 PM PDT 24
Peak memory	407936 kb
Host	smart-ded50194-bc1d-41b9-acf3-7c86dc873804
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3370284203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.3370284203 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_256.4103699510
Short name	T660
Test name
Test status
Simulation time	172949381105 ps
CPU time	2197.55 seconds
Started	Jun 04 02:24:34 PM PDT 24
Finished	Jun 04 03:01:12 PM PDT 24
Peak memory	390412 kb
Host	smart-267797d0-cdb9-44ae-9b36-bb0bc9cae81f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4103699510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.4103699510 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_384.3354728450
Short name	T233
Test name
Test status
Simulation time	113375958250 ps
CPU time	1720.79 seconds
Started	Jun 04 02:24:31 PM PDT 24
Finished	Jun 04 02:53:12 PM PDT 24
Peak memory	348036 kb
Host	smart-ab846132-755e-4561-ab4b-8fd47688b9db
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3354728450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.3354728450 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_512.4191122076
Short name	T107
Test name
Test status
Simulation time	132993800728 ps
CPU time	1274.27 seconds
Started	Jun 04 02:24:34 PM PDT 24
Finished	Jun 04 02:45:49 PM PDT 24
Peak memory	301796 kb
Host	smart-72d99fdb-74ef-46ba-a229-c5cbfb490a5a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4191122076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.4191122076 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_shake_128.4196591016
Short name	T836
Test name
Test status
Simulation time	93606823981 ps
CPU time	5092.11 seconds
Started	Jun 04 02:24:37 PM PDT 24
Finished	Jun 04 03:49:31 PM PDT 24
Peak memory	655452 kb
Host	smart-92669ea4-a7c5-4896-92fb-50599d053d01
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4196591016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.4196591016 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_shake_256.2672005053
Short name	T565
Test name
Test status
Simulation time	228024734447 ps
CPU time	5468.59 seconds
Started	Jun 04 02:24:37 PM PDT 24
Finished	Jun 04 03:55:47 PM PDT 24
Peak memory	573676 kb
Host	smart-dc3f9d41-f7ef-4db2-ac30-71caa242c1c8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2672005053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.2672005053 +enable_masking=1 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_shake_256/latest

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