Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99406231	1			T1	1832		T3	158123		T16	269
all_values[1]	99406231	1			T1	1832		T3	158123		T16	269
all_values[2]	99406231	1			T1	1832		T3	158123		T16	269

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

587704

1

T1

60

T3

26

T16

13

auto[1]

297630989

1

T1

5436

T3

474343

T16

794

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

296701401

1

T1

4722

T3

472995

T16

774

auto[1]

1517292

1

T1

774

T3

1374

T16

33

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	179089	1			T1	19		T3	3		T16	9
all_values[0]	auto[0]	auto[1]	2215	1			T1	6		T3	4		T16	4
all_values[0]	auto[1]	auto[0]	98721378	1			T1	1555		T3	157662		T16	249
all_values[0]	auto[1]	auto[1]	503549	1			T1	252		T3	454		T16	7
all_values[1]	auto[0]	auto[0]	197835	1			T7	163		T35	1		T36	1
all_values[1]	auto[0]	auto[1]	1629	1			T7	2		T35	2		T36	2
all_values[1]	auto[1]	auto[0]	98702632	1			T1	1574		T3	157665		T16	258
all_values[1]	auto[1]	auto[1]	504135	1			T1	258		T3	458		T16	11
all_values[2]	auto[0]	auto[0]	205155	1			T1	28		T3	10		T34	2
all_values[2]	auto[0]	auto[1]	1781	1			T1	7		T3	9		T34	1
all_values[2]	auto[1]	auto[0]	98695312	1			T1	1546		T3	157655		T16	258
all_values[2]	auto[1]	auto[1]	503983	1			T1	251		T3	449		T16	11