Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
373528 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
315120 |
1 |
|
|
T1 |
332 |
|
T3 |
618 |
|
T16 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172407 |
1 |
|
|
T1 |
98 |
|
T3 |
184 |
|
T16 |
2 |
lower_val |
170630 |
1 |
|
|
T1 |
66 |
|
T3 |
122 |
|
T16 |
2 |
zero_val |
1860 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
265608 |
1 |
|
|
T1 |
92 |
|
T3 |
164 |
|
T16 |
2 |
lower_val |
264762 |
1 |
|
|
T1 |
90 |
|
T2 |
2 |
|
T3 |
158 |
zero_val |
158278 |
1 |
|
|
T1 |
152 |
|
T3 |
298 |
|
T16 |
16 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
46475 |
1 |
|
|
T34 |
81 |
|
T7 |
6 |
|
T35 |
72 |
higher_val |
higher_val |
auto[1] |
19736 |
1 |
|
|
T1 |
30 |
|
T3 |
44 |
|
T7 |
11 |
higher_val |
lower_val |
auto[0] |
46373 |
1 |
|
|
T34 |
78 |
|
T7 |
7 |
|
T35 |
82 |
higher_val |
lower_val |
auto[1] |
20012 |
1 |
|
|
T1 |
29 |
|
T3 |
41 |
|
T7 |
19 |
higher_val |
zero_val |
auto[0] |
94 |
1 |
|
|
T7 |
2 |
|
T38 |
1 |
|
T40 |
1 |
higher_val |
zero_val |
auto[1] |
39717 |
1 |
|
|
T1 |
39 |
|
T3 |
99 |
|
T16 |
2 |
lower_val |
higher_val |
auto[0] |
46433 |
1 |
|
|
T1 |
1 |
|
T34 |
63 |
|
T35 |
79 |
lower_val |
higher_val |
auto[1] |
19556 |
1 |
|
|
T1 |
20 |
|
T3 |
39 |
|
T16 |
1 |
lower_val |
lower_val |
auto[0] |
45958 |
1 |
|
|
T34 |
89 |
|
T35 |
103 |
|
T8 |
4 |
lower_val |
lower_val |
auto[1] |
19715 |
1 |
|
|
T1 |
13 |
|
T3 |
31 |
|
T7 |
10 |
lower_val |
zero_val |
auto[0] |
89 |
1 |
|
|
T9 |
1 |
|
T13 |
1 |
|
T105 |
1 |
lower_val |
zero_val |
auto[1] |
38879 |
1 |
|
|
T1 |
32 |
|
T3 |
52 |
|
T16 |
1 |
zero_val |
higher_val |
auto[0] |
609 |
1 |
|
|
T1 |
1 |
|
T35 |
1 |
|
T36 |
1 |
zero_val |
higher_val |
auto[1] |
133 |
1 |
|
|
T7 |
1 |
|
T91 |
1 |
|
T208 |
1 |
zero_val |
lower_val |
auto[0] |
547 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T34 |
1 |
zero_val |
lower_val |
auto[1] |
143 |
1 |
|
|
T7 |
1 |
|
T37 |
2 |
|
T19 |
1 |
zero_val |
zero_val |
auto[0] |
262 |
1 |
|
|
T16 |
1 |
|
T7 |
2 |
|
T38 |
1 |
zero_val |
zero_val |
auto[1] |
166 |
1 |
|
|
T7 |
1 |
|
T37 |
4 |
|
T91 |
1 |