Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99406231	1			T1	1832		T3	158123		T16	269
all_pins[1]	99406231	1			T1	1832		T3	158123		T16	269
all_pins[2]	99406231	1			T1	1832		T3	158123		T16	269

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	297442559	1			T1	5244		T3	473915		T16	797
values[0x1]	776134	1			T1	252		T3	454		T16	10
transitions[0x0=>0x1]	774237	1			T1	252		T3	454		T16	10
transitions[0x1=>0x0]	774264	1			T1	252		T3	454		T16	10

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98902682	1			T1	1580		T3	157669		T16	262
all_pins[0]	values[0x1]	503549	1			T1	252		T3	454		T16	7
all_pins[0]	transitions[0x0=>0x1]	503536	1			T1	252		T3	454		T16	7
all_pins[0]	transitions[0x1=>0x0]	6141	1			T16	3		T8	1		T13	24
all_pins[1]	values[0x0]	99400077	1			T1	1832		T3	158123		T16	266
all_pins[1]	values[0x1]	6154	1			T16	3		T8	1		T13	24
all_pins[1]	transitions[0x0=>0x1]	5870	1			T16	3		T8	1		T13	18
all_pins[1]	transitions[0x1=>0x0]	266147	1			T13	1931		T55	8		T20	142
all_pins[2]	values[0x0]	99139800	1			T1	1832		T3	158123		T16	269
all_pins[2]	values[0x1]	266431	1			T13	1937		T55	8		T20	142
all_pins[2]	transitions[0x0=>0x1]	264831	1			T13	1924		T55	8		T20	141
all_pins[2]	transitions[0x1=>0x0]	501976	1			T1	252		T3	454		T16	7