Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	655	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5391	1			T7	3		T38	32		T18	2
len_601_800	12077	1			T7	19		T8	4		T38	64
len_401_600	8085	1			T7	10		T8	2		T38	43
len_201_400	16412	1			T7	3		T8	1		T38	22
len_65_200	73332	1			T1	87		T7	22		T37	685
len_min_for_xof_require_squeeze	984	1			T37	9		T90	9		T91	10
len_keccak_block_sizes[72]	743	1			T37	9		T90	9		T91	5
len_keccak_block_sizes[104]	747	1			T1	2		T37	9		T90	9
len_keccak_block_sizes[136]	744	1			T7	1		T37	9		T90	9
len_keccak_block_sizes[144]	290	1			T1	1		T91	5		T209	5
len_keccak_block_sizes[168]	279	1			T1	1		T91	5		T209	5
len_datapath_width	14235	1			T1	6		T16	3		T7	6
len_2_63	212430	1			T1	71		T3	310		T16	6
len_1	53	1			T1	3		T210	1		T211	1