Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10574849 |
1 |
|
|
T1 |
6382 |
|
T3 |
3720 |
|
T16 |
96 |
auto[1] |
10574816 |
1 |
|
|
T1 |
6382 |
|
T3 |
3720 |
|
T16 |
96 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20913607 |
1 |
|
|
T1 |
12528 |
|
T3 |
7440 |
|
T16 |
192 |
triple_byte_access |
78392 |
1 |
|
|
T1 |
68 |
|
T7 |
44 |
|
T37 |
558 |
halfword_access |
79066 |
1 |
|
|
T1 |
74 |
|
T7 |
32 |
|
T37 |
558 |
byte_access |
78600 |
1 |
|
|
T1 |
94 |
|
T7 |
30 |
|
T37 |
558 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10456820 |
1 |
|
|
T1 |
6264 |
|
T3 |
3720 |
|
T16 |
96 |
auto[0] |
triple_byte_access |
39196 |
1 |
|
|
T1 |
34 |
|
T7 |
22 |
|
T37 |
279 |
auto[0] |
halfword_access |
39533 |
1 |
|
|
T1 |
37 |
|
T7 |
16 |
|
T37 |
279 |
auto[0] |
byte_access |
39300 |
1 |
|
|
T1 |
47 |
|
T7 |
15 |
|
T37 |
279 |
auto[1] |
word_access |
10456787 |
1 |
|
|
T1 |
6264 |
|
T3 |
3720 |
|
T16 |
96 |
auto[1] |
triple_byte_access |
39196 |
1 |
|
|
T1 |
34 |
|
T7 |
22 |
|
T37 |
279 |
auto[1] |
halfword_access |
39533 |
1 |
|
|
T1 |
37 |
|
T7 |
16 |
|
T37 |
279 |
auto[1] |
byte_access |
39300 |
1 |
|
|
T1 |
47 |
|
T7 |
15 |
|
T37 |
279 |