Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101005614	1			T1	293		T2	301		T3	261013
all_values[1]	101005614	1			T1	293		T2	301		T3	261013
all_values[2]	101005614	1			T1	293		T2	301		T3	261013

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

664897

1

T1

9

T2

7

T3

10220

auto[1]

302351945

1

T1

870

T2

896

T3

772819

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301480806

1

T1

840

T2

864

T3

782325

auto[1]

1536036

1

T1

39

T2

39

T3

714

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	223229	1			T3	2814		T33	18		T22	45
all_values[0]	auto[0]	auto[1]	2166	1			T3	2		T33	12		T22	2
all_values[0]	auto[1]	auto[0]	100270373	1			T1	280		T2	288		T3	257961
all_values[0]	auto[1]	auto[1]	509846	1			T1	13		T2	13		T3	236
all_values[1]	auto[0]	auto[0]	201591	1			T1	8		T2	6		T3	2814
all_values[1]	auto[0]	auto[1]	1550	1			T1	1		T2	1		T3	2
all_values[1]	auto[1]	auto[0]	100292011	1			T1	272		T2	282		T3	257961
all_values[1]	auto[1]	auto[1]	510462	1			T1	12		T2	12		T3	236
all_values[2]	auto[0]	auto[0]	234653	1			T3	4585		T34	17		T22	549
all_values[2]	auto[0]	auto[1]	1708	1			T3	3		T34	1		T22	5
all_values[2]	auto[1]	auto[0]	100258949	1			T1	280		T2	288		T3	256190
all_values[2]	auto[1]	auto[1]	510304	1			T1	13		T2	13		T3	235