Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
419364 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
277088 |
1 |
|
|
T1 |
16 |
|
T2 |
16 |
|
T3 |
318 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174502 |
1 |
|
|
T1 |
7 |
|
T2 |
6 |
|
T3 |
68 |
lower_val |
173149 |
1 |
|
|
T2 |
3 |
|
T3 |
70 |
|
T33 |
184 |
zero_val |
1871 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
278514 |
1 |
|
|
T1 |
4 |
|
T2 |
2 |
|
T3 |
90 |
lower_val |
279438 |
1 |
|
|
T1 |
2 |
|
T2 |
4 |
|
T3 |
48 |
zero_val |
138500 |
1 |
|
|
T1 |
12 |
|
T2 |
12 |
|
T3 |
182 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
52484 |
1 |
|
|
T33 |
75 |
|
T34 |
29 |
|
T7 |
9 |
higher_val |
higher_val |
auto[1] |
17260 |
1 |
|
|
T1 |
3 |
|
T3 |
23 |
|
T22 |
6 |
higher_val |
lower_val |
auto[0] |
52849 |
1 |
|
|
T33 |
73 |
|
T34 |
31 |
|
T7 |
11 |
higher_val |
lower_val |
auto[1] |
17362 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T3 |
7 |
higher_val |
zero_val |
auto[0] |
84 |
1 |
|
|
T1 |
1 |
|
T22 |
1 |
|
T16 |
1 |
higher_val |
zero_val |
auto[1] |
34463 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
38 |
lower_val |
higher_val |
auto[0] |
51856 |
1 |
|
|
T33 |
88 |
|
T34 |
18 |
|
T35 |
1 |
lower_val |
higher_val |
auto[1] |
17215 |
1 |
|
|
T2 |
1 |
|
T3 |
16 |
|
T22 |
11 |
lower_val |
lower_val |
auto[0] |
52441 |
1 |
|
|
T33 |
96 |
|
T34 |
23 |
|
T7 |
10 |
lower_val |
lower_val |
auto[1] |
17207 |
1 |
|
|
T3 |
7 |
|
T22 |
20 |
|
T35 |
48 |
lower_val |
zero_val |
auto[0] |
85 |
1 |
|
|
T16 |
1 |
|
T18 |
2 |
|
T189 |
1 |
lower_val |
zero_val |
auto[1] |
34345 |
1 |
|
|
T2 |
2 |
|
T3 |
47 |
|
T22 |
25 |
zero_val |
higher_val |
auto[0] |
638 |
1 |
|
|
T34 |
1 |
|
T35 |
1 |
|
T37 |
1 |
zero_val |
higher_val |
auto[1] |
132 |
1 |
|
|
T16 |
2 |
|
T43 |
3 |
|
T190 |
1 |
zero_val |
lower_val |
auto[0] |
563 |
1 |
|
|
T33 |
1 |
|
T7 |
1 |
|
T38 |
3 |
zero_val |
lower_val |
auto[1] |
127 |
1 |
|
|
T16 |
1 |
|
T116 |
2 |
|
T137 |
1 |
zero_val |
zero_val |
auto[0] |
248 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
zero_val |
auto[1] |
163 |
1 |
|
|
T43 |
3 |
|
T116 |
6 |
|
T190 |
1 |