Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101005614	1			T1	293		T2	301		T3	261013
all_pins[1]	101005614	1			T1	293		T2	301		T3	261013
all_pins[2]	101005614	1			T1	293		T2	301		T3	261013

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	302218964	1			T1	866		T2	890		T3	782803
values[0x1]	797878	1			T1	13		T2	13		T3	236
transitions[0x0=>0x1]	795871	1			T1	13		T2	13		T3	236
transitions[0x1=>0x0]	795891	1			T1	13		T2	13		T3	236

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100495768	1			T1	280		T2	288		T3	260777
all_pins[0]	values[0x1]	509846	1			T1	13		T2	13		T3	236
all_pins[0]	transitions[0x0=>0x1]	509833	1			T1	13		T2	13		T3	236
all_pins[0]	transitions[0x1=>0x0]	6040	1			T22	51		T42	3		T16	84
all_pins[1]	values[0x0]	100999561	1			T1	293		T2	301		T3	261013
all_pins[1]	values[0x1]	6053	1			T22	51		T42	3		T16	84
all_pins[1]	transitions[0x0=>0x1]	5752	1			T22	51		T42	3		T16	72
all_pins[1]	transitions[0x1=>0x0]	281678	1			T9	245		T16	4832		T23	367
all_pins[2]	values[0x0]	100723635	1			T1	293		T2	301		T3	261013
all_pins[2]	values[0x1]	281979	1			T9	245		T16	4844		T23	367
all_pins[2]	transitions[0x0=>0x1]	280286	1			T9	245		T16	4819		T23	367
all_pins[2]	transitions[0x1=>0x0]	508173	1			T1	13		T2	13		T3	236