Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	688	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5455	1			T3	16		T34	13		T22	12
len_601_800	12629	1			T3	57		T34	34		T22	41
len_401_600	8228	1			T3	45		T34	26		T22	29
len_201_400	16442	1			T3	23		T34	12		T22	10
len_65_200	74202	1			T3	11		T34	7		T22	8
len_min_for_xof_require_squeeze	1006	1			T3	1		T37	1		T16	1
len_keccak_block_sizes[72]	750	1			T37	1		T16	2		T43	5
len_keccak_block_sizes[104]	757	1			T37	1		T43	5		T86	5
len_keccak_block_sizes[136]	767	1			T16	1		T43	5		T86	5
len_keccak_block_sizes[144]	295	1			T42	1		T43	5		T86	5
len_keccak_block_sizes[168]	288	1			T16	1		T43	5		T85	1
len_datapath_width	14188	1			T1	3		T2	3		T3	2
len_2_63	214677	1			T1	6		T2	6		T3	5
len_1	59	1			T37	1		T16	1		T137	1