Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98809805	1			T1	161744		T2	212633		T3	28112
all_values[1]	98809805	1			T1	161744		T2	212633		T3	28112
all_values[2]	98809805	1			T1	161744		T2	212633		T3	28112

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

541077

1

T1

30

T2

3

T29

14

auto[1]

295888338

1

T1

485202

T2

637896

T3

84336

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

294905499

1

T1

483822

T2

636234

T3

83505

auto[1]

1523916

1

T1

1410

T2

1665

T3

831

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	162929	1			T1	15		T29	5		T7	243
all_values[0]	auto[0]	auto[1]	2185	1			T1	12		T29	2		T7	2
all_values[0]	auto[1]	auto[0]	98138904	1			T1	161259		T2	212078		T3	27835
all_values[0]	auto[1]	auto[1]	505787	1			T1	458		T2	555		T3	277
all_values[1]	auto[0]	auto[0]	158608	1			T1	1		T2	2		T32	10
all_values[1]	auto[0]	auto[1]	1515	1			T1	2		T2	1		T32	5
all_values[1]	auto[1]	auto[0]	98143225	1			T1	161273		T2	212076		T3	27835
all_values[1]	auto[1]	auto[1]	506457	1			T1	468		T2	554		T3	277
all_values[2]	auto[0]	auto[0]	214299	1			T29	5		T30	4		T7	242
all_values[2]	auto[0]	auto[1]	1541	1			T29	2		T30	3		T7	2
all_values[2]	auto[1]	auto[0]	98087534	1			T1	161274		T2	212078		T3	27835
all_values[2]	auto[1]	auto[1]	506431	1			T1	470		T2	555		T3	277