Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
379826 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
394 |
auto[1] |
311414 |
1 |
|
|
T1 |
618 |
|
T2 |
746 |
|
T29 |
260 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173663 |
1 |
|
|
T1 |
148 |
|
T2 |
192 |
|
T3 |
98 |
lower_val |
171291 |
1 |
|
|
T1 |
164 |
|
T2 |
190 |
|
T3 |
87 |
zero_val |
1832 |
1 |
|
|
T1 |
3 |
|
T2 |
3 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
268236 |
1 |
|
|
T1 |
146 |
|
T2 |
182 |
|
T3 |
192 |
lower_val |
267200 |
1 |
|
|
T1 |
152 |
|
T2 |
216 |
|
T3 |
202 |
zero_val |
155804 |
1 |
|
|
T1 |
322 |
|
T2 |
350 |
|
T29 |
148 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
47287 |
1 |
|
|
T3 |
51 |
|
T7 |
9 |
|
T32 |
82 |
higher_val |
higher_val |
auto[1] |
19722 |
1 |
|
|
T1 |
36 |
|
T2 |
47 |
|
T29 |
19 |
higher_val |
lower_val |
auto[0] |
47715 |
1 |
|
|
T3 |
47 |
|
T7 |
13 |
|
T32 |
86 |
higher_val |
lower_val |
auto[1] |
19681 |
1 |
|
|
T1 |
42 |
|
T2 |
63 |
|
T29 |
11 |
higher_val |
zero_val |
auto[0] |
82 |
1 |
|
|
T30 |
1 |
|
T8 |
3 |
|
T197 |
1 |
higher_val |
zero_val |
auto[1] |
39176 |
1 |
|
|
T1 |
70 |
|
T2 |
82 |
|
T29 |
39 |
lower_val |
higher_val |
auto[0] |
47164 |
1 |
|
|
T3 |
42 |
|
T7 |
25 |
|
T32 |
79 |
lower_val |
higher_val |
auto[1] |
19391 |
1 |
|
|
T1 |
44 |
|
T2 |
50 |
|
T29 |
9 |
lower_val |
lower_val |
auto[0] |
47192 |
1 |
|
|
T3 |
45 |
|
T7 |
20 |
|
T32 |
87 |
lower_val |
lower_val |
auto[1] |
19101 |
1 |
|
|
T1 |
33 |
|
T2 |
44 |
|
T29 |
11 |
lower_val |
zero_val |
auto[0] |
81 |
1 |
|
|
T8 |
1 |
|
T198 |
1 |
|
T67 |
2 |
lower_val |
zero_val |
auto[1] |
38362 |
1 |
|
|
T1 |
87 |
|
T2 |
96 |
|
T29 |
36 |
zero_val |
higher_val |
auto[0] |
568 |
1 |
|
|
T1 |
1 |
|
T8 |
1 |
|
T33 |
1 |
zero_val |
higher_val |
auto[1] |
150 |
1 |
|
|
T2 |
1 |
|
T8 |
1 |
|
T199 |
4 |
zero_val |
lower_val |
auto[0] |
551 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T7 |
1 |
zero_val |
lower_val |
auto[1] |
116 |
1 |
|
|
T1 |
2 |
|
T8 |
1 |
|
T15 |
3 |
zero_val |
zero_val |
auto[0] |
242 |
1 |
|
|
T29 |
1 |
|
T30 |
1 |
|
T63 |
1 |
zero_val |
zero_val |
auto[1] |
205 |
1 |
|
|
T2 |
1 |
|
T15 |
3 |
|
T36 |
1 |