Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98809805	1			T1	161744		T2	212633		T3	28112
all_pins[1]	98809805	1			T1	161744		T2	212633		T3	28112
all_pins[2]	98809805	1			T1	161744		T2	212633		T3	28112

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	295661492	1			T1	484774		T2	637344		T3	83202
values[0x1]	767923	1			T1	458		T2	555		T3	1134
transitions[0x0=>0x1]	766107	1			T1	458		T2	555		T3	1134
transitions[0x1=>0x0]	766134	1			T1	458		T2	555		T3	1134

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98304018	1			T1	161286		T2	212078		T3	27835
all_pins[0]	values[0x1]	505787	1			T1	458		T2	555		T3	277
all_pins[0]	transitions[0x0=>0x1]	505777	1			T1	458		T2	555		T3	277
all_pins[0]	transitions[0x1=>0x0]	5821	1			T7	18		T33	18		T62	70
all_pins[1]	values[0x0]	98803974	1			T1	161744		T2	212633		T3	28112
all_pins[1]	values[0x1]	5831	1			T7	18		T33	18		T62	70
all_pins[1]	transitions[0x0=>0x1]	5586	1			T7	18		T33	18		T62	70
all_pins[1]	transitions[0x1=>0x0]	256060	1			T3	857		T8	4123		T15	1024
all_pins[2]	values[0x0]	98553500	1			T1	161744		T2	212633		T3	27255
all_pins[2]	values[0x1]	256305	1			T3	857		T8	4123		T15	1024
all_pins[2]	transitions[0x0=>0x1]	254744	1			T3	857		T8	4094		T15	1017
all_pins[2]	transitions[0x1=>0x0]	504253	1			T1	458		T2	555		T3	277