Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10532193 |
1 |
|
|
T1 |
3720 |
|
T2 |
2992 |
|
T3 |
33243 |
auto[1] |
10532140 |
1 |
|
|
T1 |
3720 |
|
T2 |
2992 |
|
T3 |
33243 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20827821 |
1 |
|
|
T1 |
7440 |
|
T2 |
5984 |
|
T3 |
66226 |
triple_byte_access |
78736 |
1 |
|
|
T3 |
82 |
|
T29 |
56 |
|
T7 |
26 |
halfword_access |
78996 |
1 |
|
|
T3 |
82 |
|
T29 |
56 |
|
T7 |
24 |
byte_access |
78780 |
1 |
|
|
T3 |
96 |
|
T29 |
54 |
|
T7 |
32 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10413937 |
1 |
|
|
T1 |
3720 |
|
T2 |
2992 |
|
T3 |
33113 |
auto[0] |
triple_byte_access |
39368 |
1 |
|
|
T3 |
41 |
|
T29 |
28 |
|
T7 |
13 |
auto[0] |
halfword_access |
39498 |
1 |
|
|
T3 |
41 |
|
T29 |
28 |
|
T7 |
12 |
auto[0] |
byte_access |
39390 |
1 |
|
|
T3 |
48 |
|
T29 |
27 |
|
T7 |
16 |
auto[1] |
word_access |
10413884 |
1 |
|
|
T1 |
3720 |
|
T2 |
2992 |
|
T3 |
33113 |
auto[1] |
triple_byte_access |
39368 |
1 |
|
|
T3 |
41 |
|
T29 |
28 |
|
T7 |
13 |
auto[1] |
halfword_access |
39498 |
1 |
|
|
T3 |
41 |
|
T29 |
28 |
|
T7 |
12 |
auto[1] |
byte_access |
39390 |
1 |
|
|
T3 |
48 |
|
T29 |
27 |
|
T7 |
16 |