Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99024092	1			T1	427		T2	56568		T3	162341
all_values[1]	99024092	1			T1	427		T2	56568		T3	162341
all_values[2]	99024092	1			T1	427		T2	56568		T3	162341

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

570714

1

T1

51

T2

3590

T3

21

auto[1]

296501562

1

T1

1230

T2

166114

T3

487002

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295541598

1

T1

1074

T2

168561

T3

485634

auto[1]

1530678

1

T1

207

T2

1143

T3

1389

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	204914	1			T1	31		T2	2179		T3	3
all_values[0]	auto[0]	auto[1]	2231	1			T1	8		T2	16		T3	4
all_values[0]	auto[1]	auto[0]	98308952	1			T1	327		T2	54008		T3	161875
all_values[0]	auto[1]	auto[1]	507995	1			T1	61		T2	365		T3	459
all_values[1]	auto[0]	auto[0]	172232	1			T1	10		T2	685		T3	6
all_values[1]	auto[0]	auto[1]	1704	1			T1	2		T2	20		T3	5
all_values[1]	auto[1]	auto[0]	98341634	1			T1	348		T2	55502		T3	161872
all_values[1]	auto[1]	auto[1]	508522	1			T1	67		T2	361		T3	458
all_values[2]	auto[0]	auto[0]	187976	1			T2	677		T3	1		T30	1
all_values[2]	auto[0]	auto[1]	1657	1			T2	13		T3	2		T30	2
all_values[2]	auto[1]	auto[0]	98325890	1			T1	358		T2	55510		T3	161877
all_values[2]	auto[1]	auto[1]	508569	1			T1	69		T2	368		T3	461