Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
392164 |
1 |
|
|
T1 |
2 |
|
T2 |
394 |
|
T3 |
620 |
auto[1] |
301962 |
1 |
|
|
T1 |
82 |
|
T2 |
152 |
|
T30 |
746 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173809 |
1 |
|
|
T1 |
28 |
|
T2 |
143 |
|
T3 |
141 |
lower_val |
171692 |
1 |
|
|
T1 |
15 |
|
T2 |
124 |
|
T3 |
176 |
zero_val |
2030 |
1 |
|
|
T1 |
1 |
|
T2 |
12 |
|
T3 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
271124 |
1 |
|
|
T1 |
18 |
|
T2 |
186 |
|
T3 |
330 |
lower_val |
271176 |
1 |
|
|
T1 |
18 |
|
T2 |
272 |
|
T3 |
290 |
zero_val |
151826 |
1 |
|
|
T1 |
48 |
|
T2 |
88 |
|
T30 |
380 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
49050 |
1 |
|
|
T2 |
43 |
|
T3 |
83 |
|
T31 |
84 |
higher_val |
higher_val |
auto[1] |
18834 |
1 |
|
|
T1 |
5 |
|
T2 |
7 |
|
T30 |
49 |
higher_val |
lower_val |
auto[0] |
49217 |
1 |
|
|
T2 |
59 |
|
T3 |
58 |
|
T31 |
62 |
higher_val |
lower_val |
auto[1] |
18864 |
1 |
|
|
T1 |
6 |
|
T2 |
11 |
|
T30 |
62 |
higher_val |
zero_val |
auto[0] |
97 |
1 |
|
|
T2 |
1 |
|
T20 |
1 |
|
T97 |
1 |
higher_val |
zero_val |
auto[1] |
37747 |
1 |
|
|
T1 |
17 |
|
T2 |
22 |
|
T30 |
95 |
lower_val |
higher_val |
auto[0] |
48720 |
1 |
|
|
T2 |
41 |
|
T3 |
94 |
|
T31 |
69 |
lower_val |
higher_val |
auto[1] |
18533 |
1 |
|
|
T1 |
4 |
|
T2 |
8 |
|
T30 |
44 |
lower_val |
lower_val |
auto[0] |
48723 |
1 |
|
|
T2 |
53 |
|
T3 |
82 |
|
T31 |
77 |
lower_val |
lower_val |
auto[1] |
18445 |
1 |
|
|
T1 |
3 |
|
T2 |
8 |
|
T30 |
45 |
lower_val |
zero_val |
auto[0] |
101 |
1 |
|
|
T2 |
1 |
|
T30 |
1 |
|
T16 |
1 |
lower_val |
zero_val |
auto[1] |
37170 |
1 |
|
|
T1 |
8 |
|
T2 |
13 |
|
T30 |
100 |
zero_val |
higher_val |
auto[0] |
590 |
1 |
|
|
T2 |
4 |
|
T3 |
1 |
|
T31 |
3 |
zero_val |
higher_val |
auto[1] |
172 |
1 |
|
|
T2 |
2 |
|
T36 |
2 |
|
T15 |
3 |
zero_val |
lower_val |
auto[0] |
620 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T7 |
1 |
zero_val |
lower_val |
auto[1] |
153 |
1 |
|
|
T2 |
1 |
|
T36 |
1 |
|
T72 |
3 |
zero_val |
zero_val |
auto[0] |
272 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T30 |
1 |
zero_val |
zero_val |
auto[1] |
223 |
1 |
|
|
T2 |
1 |
|
T36 |
3 |
|
T15 |
3 |