Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99024092	1			T1	427		T2	56568		T3	162341
all_pins[1]	99024092	1			T1	427		T2	56568		T3	162341
all_pins[2]	99024092	1			T1	427		T2	56568		T3	162341

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	296171345	1			T1	1220		T2	160122		T3	486564
values[0x1]	900931	1			T1	61		T2	9582		T3	459
transitions[0x0=>0x1]	898373	1			T1	61		T2	9519		T3	459
transitions[0x1=>0x0]	898391	1			T1	61		T2	9519		T3	459

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98516097	1			T1	366		T2	56203		T3	161882
all_pins[0]	values[0x1]	507995	1			T1	61		T2	365		T3	459
all_pins[0]	transitions[0x0=>0x1]	507982	1			T1	61		T2	365		T3	459
all_pins[0]	transitions[0x1=>0x0]	5748	1			T32	53		T35	1		T76	78
all_pins[1]	values[0x0]	99018331	1			T1	427		T2	56568		T3	162341
all_pins[1]	values[0x1]	5761	1			T32	53		T35	1		T76	78
all_pins[1]	transitions[0x0=>0x1]	5505	1			T32	53		T35	1		T76	78
all_pins[1]	transitions[0x1=>0x0]	386919	1			T2	9217		T7	264		T20	5
all_pins[2]	values[0x0]	98636917	1			T1	427		T2	47351		T3	162341
all_pins[2]	values[0x1]	387175	1			T2	9217		T7	264		T20	5
all_pins[2]	transitions[0x0=>0x1]	384886	1			T2	9154		T7	264		T20	5
all_pins[2]	transitions[0x1=>0x0]	505724	1			T1	61		T2	302		T3	459