Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	727	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5867	1			T2	31		T7	3		T32	21
len_601_800	13479	1			T2	67		T7	13		T32	73
len_401_600	8875	1			T2	47		T7	11		T32	52
len_201_400	16664	1			T2	19		T7	3		T32	14
len_65_200	73684	1			T1	22		T2	28		T7	1
len_min_for_xof_require_squeeze	1016	1			T2	1		T36	9		T76	1
len_keccak_block_sizes[72]	754	1			T32	1		T36	9		T78	1
len_keccak_block_sizes[104]	750	1			T36	9		T77	5		T177	9
len_keccak_block_sizes[136]	748	1			T36	9		T78	1		T77	5
len_keccak_block_sizes[144]	287	1			T78	1		T77	5		T178	1
len_keccak_block_sizes[168]	290	1			T78	1		T94	1		T77	5
len_datapath_width	14301	1			T1	1		T2	13		T32	2
len_2_63	211906	1			T1	19		T2	64		T3	310
len_1	45	1			T78	2		T15	1		T72	1