Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11140673 |
1 |
|
|
T1 |
1554 |
|
T2 |
33742 |
|
T3 |
3720 |
auto[1] |
11140626 |
1 |
|
|
T1 |
1554 |
|
T2 |
33742 |
|
T3 |
3720 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
22040159 |
1 |
|
|
T1 |
3054 |
|
T2 |
67172 |
|
T3 |
7440 |
triple_byte_access |
80272 |
1 |
|
|
T1 |
14 |
|
T2 |
112 |
|
T7 |
24 |
halfword_access |
80608 |
1 |
|
|
T1 |
14 |
|
T2 |
92 |
|
T7 |
22 |
byte_access |
80260 |
1 |
|
|
T1 |
26 |
|
T2 |
108 |
|
T7 |
16 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
11020103 |
1 |
|
|
T1 |
1527 |
|
T2 |
33586 |
|
T3 |
3720 |
auto[0] |
triple_byte_access |
40136 |
1 |
|
|
T1 |
7 |
|
T2 |
56 |
|
T7 |
12 |
auto[0] |
halfword_access |
40304 |
1 |
|
|
T1 |
7 |
|
T2 |
46 |
|
T7 |
11 |
auto[0] |
byte_access |
40130 |
1 |
|
|
T1 |
13 |
|
T2 |
54 |
|
T7 |
8 |
auto[1] |
word_access |
11020056 |
1 |
|
|
T1 |
1527 |
|
T2 |
33586 |
|
T3 |
3720 |
auto[1] |
triple_byte_access |
40136 |
1 |
|
|
T1 |
7 |
|
T2 |
56 |
|
T7 |
12 |
auto[1] |
halfword_access |
40304 |
1 |
|
|
T1 |
7 |
|
T2 |
46 |
|
T7 |
11 |
auto[1] |
byte_access |
40130 |
1 |
|
|
T1 |
13 |
|
T2 |
54 |
|
T7 |
8 |