Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99853457	1			T1	2		T2	2717		T3	1295
all_values[1]	99853457	1			T1	2		T2	2717		T3	1295
all_values[2]	99853457	1			T1	2		T2	2717		T3	1295

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

577693

1

T1

2

T2

596

T21

3

auto[1]

298982678

1

T1

4

T2

7555

T3

3885

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298026885

1

T1

6

T2

8076

T3

3834

auto[1]

1533486

1

T2

75

T3

51

T21

1110

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	151525	1			T2	413		T37	1		T35	2974
all_values[0]	auto[0]	auto[1]	2090	1			T2	6		T37	2		T35	2
all_values[0]	auto[1]	auto[0]	99190770	1			T1	2		T2	2279		T3	1278
all_values[0]	auto[1]	auto[1]	509072	1			T2	19		T3	17		T21	370
all_values[1]	auto[0]	auto[0]	231629	1			T2	175		T36	37		T37	1
all_values[1]	auto[0]	auto[1]	1754	1			T2	2		T36	15		T37	2
all_values[1]	auto[1]	auto[0]	99110666	1			T1	2		T2	2517		T3	1278
all_values[1]	auto[1]	auto[1]	509408	1			T2	23		T3	17		T21	370
all_values[2]	auto[0]	auto[0]	189118	1			T1	2		T21	2		T35	2974
all_values[2]	auto[0]	auto[1]	1577	1			T21	1		T35	2		T39	3
all_values[2]	auto[1]	auto[0]	99153177	1			T2	2692		T3	1278		T21	107713
all_values[2]	auto[1]	auto[1]	509585	1			T2	25		T3	17		T21	369