Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
372512 |
1 |
|
|
T1 |
2 |
|
T2 |
50 |
|
T3 |
2 |
auto[1] |
322462 |
1 |
|
|
T3 |
20 |
|
T36 |
618 |
|
T7 |
128 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174753 |
1 |
|
|
T2 |
6 |
|
T3 |
4 |
|
T21 |
110 |
lower_val |
171986 |
1 |
|
|
T2 |
16 |
|
T3 |
4 |
|
T21 |
116 |
zero_val |
1889 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
266304 |
1 |
|
|
T1 |
2 |
|
T2 |
32 |
|
T3 |
12 |
lower_val |
267240 |
1 |
|
|
T2 |
18 |
|
T3 |
4 |
|
T21 |
212 |
zero_val |
161430 |
1 |
|
|
T3 |
6 |
|
T36 |
308 |
|
T7 |
56 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
46591 |
1 |
|
|
T2 |
5 |
|
T21 |
69 |
|
T37 |
563 |
higher_val |
higher_val |
auto[1] |
20291 |
1 |
|
|
T3 |
1 |
|
T36 |
33 |
|
T7 |
9 |
higher_val |
lower_val |
auto[0] |
46901 |
1 |
|
|
T2 |
1 |
|
T21 |
41 |
|
T37 |
569 |
higher_val |
lower_val |
auto[1] |
20228 |
1 |
|
|
T3 |
1 |
|
T36 |
46 |
|
T7 |
13 |
higher_val |
zero_val |
auto[0] |
84 |
1 |
|
|
T7 |
1 |
|
T23 |
1 |
|
T115 |
1 |
higher_val |
zero_val |
auto[1] |
40658 |
1 |
|
|
T3 |
2 |
|
T36 |
67 |
|
T7 |
19 |
lower_val |
higher_val |
auto[0] |
45712 |
1 |
|
|
T2 |
12 |
|
T21 |
62 |
|
T37 |
592 |
lower_val |
higher_val |
auto[1] |
19955 |
1 |
|
|
T3 |
2 |
|
T36 |
47 |
|
T7 |
8 |
lower_val |
lower_val |
auto[0] |
46171 |
1 |
|
|
T2 |
4 |
|
T21 |
54 |
|
T37 |
555 |
lower_val |
lower_val |
auto[1] |
20168 |
1 |
|
|
T3 |
2 |
|
T36 |
29 |
|
T7 |
14 |
lower_val |
zero_val |
auto[0] |
87 |
1 |
|
|
T39 |
1 |
|
T42 |
1 |
|
T18 |
1 |
lower_val |
zero_val |
auto[1] |
39893 |
1 |
|
|
T36 |
80 |
|
T7 |
12 |
|
T39 |
79 |
zero_val |
higher_val |
auto[0] |
596 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T21 |
1 |
zero_val |
higher_val |
auto[1] |
153 |
1 |
|
|
T88 |
1 |
|
T15 |
2 |
|
T115 |
1 |
zero_val |
lower_val |
auto[0] |
584 |
1 |
|
|
T2 |
1 |
|
T37 |
4 |
|
T35 |
1 |
zero_val |
lower_val |
auto[1] |
132 |
1 |
|
|
T88 |
1 |
|
T15 |
1 |
|
T16 |
2 |
zero_val |
zero_val |
auto[0] |
254 |
1 |
|
|
T36 |
1 |
|
T7 |
1 |
|
T39 |
1 |
zero_val |
zero_val |
auto[1] |
170 |
1 |
|
|
T88 |
4 |
|
T15 |
4 |
|
T115 |
1 |