Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99853457	1			T1	2		T2	2717		T3	1295
all_pins[1]	99853457	1			T1	2		T2	2717		T3	1295
all_pins[2]	99853457	1			T1	2		T2	2717		T3	1295

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298696366	1			T1	6		T2	8132		T3	3866
values[0x1]	864005	1			T2	19		T3	19		T21	370
transitions[0x0=>0x1]	861540	1			T2	19		T3	19		T21	370
transitions[0x1=>0x0]	861568	1			T2	19		T3	19		T21	370

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99344385	1			T1	2		T2	2698		T3	1278
all_pins[0]	values[0x1]	509072	1			T2	19		T3	17		T21	370
all_pins[0]	transitions[0x0=>0x1]	509057	1			T2	19		T3	17		T21	370
all_pins[0]	transitions[0x1=>0x0]	6246	1			T35	28		T7	8		T8	15
all_pins[1]	values[0x0]	99847196	1			T1	2		T2	2717		T3	1295
all_pins[1]	values[0x1]	6261	1			T35	28		T7	8		T8	15
all_pins[1]	transitions[0x0=>0x1]	5966	1			T35	28		T7	8		T8	15
all_pins[1]	transitions[0x1=>0x0]	348377	1			T3	2		T14	11663		T22	24
all_pins[2]	values[0x0]	99504785	1			T1	2		T2	2717		T3	1293
all_pins[2]	values[0x1]	348672	1			T3	2		T14	11663		T22	24
all_pins[2]	transitions[0x0=>0x1]	346517	1			T3	2		T14	11583		T22	24
all_pins[2]	transitions[0x1=>0x0]	506945	1			T2	19		T3	17		T21	370