Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
341036 |
1 |
|
|
T1 |
1 |
|
T2 |
28 |
|
T3 |
11 |
auto[1] |
3324 |
1 |
|
|
T2 |
6 |
|
T4 |
1 |
|
T7 |
10 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
306281 |
1 |
|
|
T1 |
1 |
|
T2 |
12 |
|
T3 |
4 |
auto[1] |
38079 |
1 |
|
|
T2 |
22 |
|
T3 |
7 |
|
T4 |
1 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
330658 |
1 |
|
|
T1 |
1 |
|
T2 |
20 |
|
T3 |
10 |
auto[1] |
13702 |
1 |
|
|
T2 |
14 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13702 |
1 |
|
|
T2 |
14 |
|
T3 |
1 |
|
T4 |
1 |
sw_kmac_invalid_sideload |
330658 |
1 |
|
|
T1 |
1 |
|
T2 |
20 |
|
T3 |
10 |
app_valid_sideload |
13702 |
1 |
|
|
T2 |
14 |
|
T3 |
1 |
|
T4 |
1 |
app_invalid_sideload |
330658 |
1 |
|
|
T1 |
1 |
|
T2 |
20 |
|
T3 |
10 |