Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10717953 |
1 |
|
|
T2 |
3047 |
|
T3 |
1722 |
|
T21 |
3936 |
auto[1] |
10717929 |
1 |
|
|
T2 |
3047 |
|
T3 |
1722 |
|
T21 |
3936 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21196950 |
1 |
|
|
T2 |
6066 |
|
T3 |
3432 |
|
T21 |
7872 |
triple_byte_access |
79366 |
1 |
|
|
T2 |
6 |
|
T3 |
2 |
|
T37 |
620 |
halfword_access |
80166 |
1 |
|
|
T2 |
12 |
|
T3 |
6 |
|
T37 |
632 |
byte_access |
79400 |
1 |
|
|
T2 |
10 |
|
T3 |
4 |
|
T37 |
620 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10598487 |
1 |
|
|
T2 |
3033 |
|
T3 |
1716 |
|
T21 |
3936 |
auto[0] |
triple_byte_access |
39683 |
1 |
|
|
T2 |
3 |
|
T3 |
1 |
|
T37 |
310 |
auto[0] |
halfword_access |
40083 |
1 |
|
|
T2 |
6 |
|
T3 |
3 |
|
T37 |
316 |
auto[0] |
byte_access |
39700 |
1 |
|
|
T2 |
5 |
|
T3 |
2 |
|
T37 |
310 |
auto[1] |
word_access |
10598463 |
1 |
|
|
T2 |
3033 |
|
T3 |
1716 |
|
T21 |
3936 |
auto[1] |
triple_byte_access |
39683 |
1 |
|
|
T2 |
3 |
|
T3 |
1 |
|
T37 |
310 |
auto[1] |
halfword_access |
40083 |
1 |
|
|
T2 |
6 |
|
T3 |
3 |
|
T37 |
316 |
auto[1] |
byte_access |
39700 |
1 |
|
|
T2 |
5 |
|
T3 |
2 |
|
T37 |
310 |