Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98684322	1			T2	2		T3	566010		T16	161157
all_values[1]	98684322	1			T2	2		T3	566010		T16	161157
all_values[2]	98684322	1			T2	2		T3	566010		T16	161157

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

693983

1

T3

21

T16

11

T21

156

auto[1]

295358983

1

T2

6

T3

169800

T16

483460

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

294543354

1

T2

6

T3

168764

T16

482088

auto[1]

1509612

1

T3

10386

T16

1383

T21

45

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	221238	1			T3	3		T16	5		T35	10
all_values[0]	auto[0]	auto[1]	2181	1			T3	4		T16	6		T35	2
all_values[0]	auto[1]	auto[0]	97959880	1			T2	2		T3	562545		T16	160691
all_values[0]	auto[1]	auto[1]	501023	1			T3	3458		T16	455		T21	15
all_values[1]	auto[0]	auto[0]	262676	1			T3	1		T35	10		T36	9
all_values[1]	auto[0]	auto[1]	1677	1			T3	2		T35	2		T36	6
all_values[1]	auto[1]	auto[0]	97918442	1			T2	2		T3	562547		T16	160696
all_values[1]	auto[1]	auto[1]	501527	1			T3	3460		T16	461		T21	15
all_values[2]	auto[0]	auto[0]	204512	1			T3	6		T21	145		T36	5
all_values[2]	auto[0]	auto[1]	1699	1			T3	5		T21	11		T36	2
all_values[2]	auto[1]	auto[0]	97976606	1			T2	2		T3	562542		T16	160696
all_values[2]	auto[1]	auto[1]	501505	1			T3	3457		T16	461		T21	4