Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
367450 |
1 |
|
|
T2 |
2 |
|
T3 |
2 |
|
T16 |
620 |
auto[1] |
317438 |
1 |
|
|
T3 |
4672 |
|
T36 |
618 |
|
T6 |
336 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
171769 |
1 |
|
|
T3 |
1128 |
|
T16 |
142 |
|
T21 |
6 |
lower_val |
169460 |
1 |
|
|
T2 |
1 |
|
T3 |
1187 |
|
T16 |
143 |
zero_val |
1808 |
1 |
|
|
T2 |
1 |
|
T3 |
3 |
|
T16 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
263066 |
1 |
|
|
T2 |
2 |
|
T3 |
1160 |
|
T16 |
300 |
lower_val |
262908 |
1 |
|
|
T3 |
1148 |
|
T16 |
320 |
|
T21 |
4 |
zero_val |
158914 |
1 |
|
|
T3 |
2366 |
|
T36 |
296 |
|
T6 |
170 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45895 |
1 |
|
|
T16 |
75 |
|
T21 |
5 |
|
T35 |
23 |
higher_val |
higher_val |
auto[1] |
19931 |
1 |
|
|
T3 |
276 |
|
T36 |
36 |
|
T6 |
15 |
higher_val |
lower_val |
auto[0] |
45884 |
1 |
|
|
T16 |
67 |
|
T21 |
1 |
|
T35 |
49 |
higher_val |
lower_val |
auto[1] |
20103 |
1 |
|
|
T3 |
275 |
|
T36 |
39 |
|
T6 |
28 |
higher_val |
zero_val |
auto[0] |
87 |
1 |
|
|
T6 |
1 |
|
T10 |
3 |
|
T14 |
2 |
higher_val |
zero_val |
auto[1] |
39869 |
1 |
|
|
T3 |
577 |
|
T36 |
74 |
|
T6 |
35 |
lower_val |
higher_val |
auto[0] |
45620 |
1 |
|
|
T2 |
1 |
|
T16 |
70 |
|
T21 |
1 |
lower_val |
higher_val |
auto[1] |
19452 |
1 |
|
|
T3 |
301 |
|
T36 |
51 |
|
T6 |
24 |
lower_val |
lower_val |
auto[0] |
45467 |
1 |
|
|
T16 |
73 |
|
T21 |
1 |
|
T35 |
37 |
lower_val |
lower_val |
auto[1] |
19615 |
1 |
|
|
T3 |
279 |
|
T36 |
35 |
|
T6 |
22 |
lower_val |
zero_val |
auto[0] |
102 |
1 |
|
|
T6 |
2 |
|
T37 |
1 |
|
T10 |
1 |
lower_val |
zero_val |
auto[1] |
39204 |
1 |
|
|
T3 |
607 |
|
T36 |
72 |
|
T6 |
35 |
zero_val |
higher_val |
auto[0] |
562 |
1 |
|
|
T2 |
1 |
|
T16 |
1 |
|
T21 |
1 |
zero_val |
higher_val |
auto[1] |
128 |
1 |
|
|
T6 |
2 |
|
T76 |
1 |
|
T66 |
1 |
zero_val |
lower_val |
auto[0] |
551 |
1 |
|
|
T35 |
1 |
|
T6 |
4 |
|
T50 |
1 |
zero_val |
lower_val |
auto[1] |
134 |
1 |
|
|
T3 |
2 |
|
T6 |
2 |
|
T76 |
1 |
zero_val |
zero_val |
auto[0] |
259 |
1 |
|
|
T3 |
1 |
|
T37 |
1 |
|
T48 |
1 |
zero_val |
zero_val |
auto[1] |
174 |
1 |
|
|
T6 |
1 |
|
T37 |
2 |
|
T14 |
1 |