Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10153	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8976	1			T3	30		T16	24		T35	23
len_5001_7500	14331	1			T3	30		T16	24		T35	102
len_2501_5000	9203	1			T3	30		T16	24		T35	21
len_1025_2500	5349	1			T3	16		T16	14		T35	13
len_769_1024	6034	1			T3	4		T16	2		T36	2
len_513_768	6427	1			T3	2		T16	3		T35	2
len_257_512	20634	1			T3	244		T16	2		T35	1
len_0_256	254237	1			T3	1897		T16	211		T21	9
len_keccak_block_sizes[72]	712	1			T3	3		T16	2		T36	2
len_keccak_block_sizes[104]	611	1			T3	3		T16	2		T36	2
len_keccak_block_sizes[136]	506	1			T3	3		T37	2		T50	3
len_keccak_block_sizes[144]	419	1			T3	3		T50	3		T68	3
len_keccak_block_sizes[168]	323	1			T3	3		T50	3		T68	3
len_1	749	1			T3	3		T16	2		T36	2
len_0	1188	1			T3	3		T16	2		T35	2