Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98684322	1			T2	2		T3	566010		T16	161157
all_pins[1]	98684322	1			T2	2		T3	566010		T16	161157
all_pins[2]	98684322	1			T2	2		T3	566010		T16	161157

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	295227537	1			T2	6		T3	169457		T16	483016
values[0x1]	825429	1			T3	3458		T16	455		T21	16
transitions[0x0=>0x1]	823084	1			T3	3458		T16	455		T21	16
transitions[0x1=>0x0]	823106	1			T3	3458		T16	455		T21	16

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98183299	1			T2	2		T3	562552		T16	160702
all_pins[0]	values[0x1]	501023	1			T3	3458		T16	455		T21	15
all_pins[0]	transitions[0x0=>0x1]	501007	1			T3	3458		T16	455		T21	15
all_pins[0]	transitions[0x1=>0x0]	5945	1			T21	1		T6	40		T9	60
all_pins[1]	values[0x0]	98678361	1			T2	2		T3	566010		T16	161157
all_pins[1]	values[0x1]	5961	1			T21	1		T6	40		T9	60
all_pins[1]	transitions[0x0=>0x1]	5569	1			T21	1		T6	40		T9	60
all_pins[1]	transitions[0x1=>0x0]	318053	1			T9	902		T10	3698		T19	1895
all_pins[2]	values[0x0]	98365877	1			T2	2		T3	566010		T16	161157
all_pins[2]	values[0x1]	318445	1			T9	902		T10	3703		T19	1895
all_pins[2]	transitions[0x0=>0x1]	316508	1			T9	902		T10	3681		T19	1895
all_pins[2]	transitions[0x1=>0x0]	499108	1			T3	3458		T16	455		T21	15