Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10561884 |
1 |
|
|
T3 |
27235 |
|
T16 |
3720 |
|
T21 |
96 |
auto[1] |
10561875 |
1 |
|
|
T3 |
27235 |
|
T16 |
3720 |
|
T21 |
96 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20889087 |
1 |
|
|
T3 |
52796 |
|
T16 |
7440 |
|
T21 |
192 |
triple_byte_access |
78130 |
1 |
|
|
T3 |
558 |
|
T35 |
102 |
|
T6 |
128 |
halfword_access |
78446 |
1 |
|
|
T3 |
558 |
|
T35 |
76 |
|
T6 |
110 |
byte_access |
78096 |
1 |
|
|
T3 |
558 |
|
T35 |
94 |
|
T6 |
128 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10444548 |
1 |
|
|
T3 |
26398 |
|
T16 |
3720 |
|
T21 |
96 |
auto[0] |
triple_byte_access |
39065 |
1 |
|
|
T3 |
279 |
|
T35 |
51 |
|
T6 |
64 |
auto[0] |
halfword_access |
39223 |
1 |
|
|
T3 |
279 |
|
T35 |
38 |
|
T6 |
55 |
auto[0] |
byte_access |
39048 |
1 |
|
|
T3 |
279 |
|
T35 |
47 |
|
T6 |
64 |
auto[1] |
word_access |
10444539 |
1 |
|
|
T3 |
26398 |
|
T16 |
3720 |
|
T21 |
96 |
auto[1] |
triple_byte_access |
39065 |
1 |
|
|
T3 |
279 |
|
T35 |
51 |
|
T6 |
64 |
auto[1] |
halfword_access |
39223 |
1 |
|
|
T3 |
279 |
|
T35 |
38 |
|
T6 |
55 |
auto[1] |
byte_access |
39048 |
1 |
|
|
T3 |
279 |
|
T35 |
47 |
|
T6 |
64 |