Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100955447	1			T2	14774		T3	209224		T17	271
all_values[1]	100955447	1			T2	14774		T3	209224		T17	271
all_values[2]	100955447	1			T2	14774		T3	209224		T17	271

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

623656

1

T2

155

T3

41

T17

18

auto[1]

302242685

1

T2

44167

T3

627631

T17

795

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301328868

1

T2

43878

T3

625992

T17

774

auto[1]

1537473

1

T2

444

T3

1680

T17

39

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	233254	1			T3	9		T34	3		T19	637
all_values[0]	auto[0]	auto[1]	2235	1			T3	10		T34	4		T19	8
all_values[0]	auto[1]	auto[0]	100209702	1			T2	14626		T3	208655		T17	258
all_values[0]	auto[1]	auto[1]	510256	1			T2	148		T3	550		T17	13
all_values[1]	auto[0]	auto[0]	174454	1			T2	154		T3	3		T17	5
all_values[1]	auto[0]	auto[1]	1556	1			T2	1		T3	4		T17	1
all_values[1]	auto[1]	auto[0]	100268502	1			T2	14472		T3	208661		T17	253
all_values[1]	auto[1]	auto[1]	510935	1			T2	147		T3	556		T17	12
all_values[2]	auto[0]	auto[0]	210491	1			T3	7		T17	10		T7	205
all_values[2]	auto[0]	auto[1]	1666	1			T3	8		T17	2		T7	2
all_values[2]	auto[1]	auto[0]	100232465	1			T2	14626		T3	208657		T17	248
all_values[2]	auto[1]	auto[1]	510825	1			T2	148		T3	552		T17	11