Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
387564 |
1 |
|
|
T2 |
2 |
|
T3 |
748 |
|
T17 |
2 |
auto[1] |
309120 |
1 |
|
|
T2 |
256 |
|
T17 |
16 |
|
T33 |
490 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173845 |
1 |
|
|
T2 |
64 |
|
T3 |
194 |
|
T17 |
4 |
lower_val |
173262 |
1 |
|
|
T2 |
68 |
|
T3 |
182 |
|
T17 |
6 |
zero_val |
1869 |
1 |
|
|
T2 |
3 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
270346 |
1 |
|
|
T2 |
76 |
|
T3 |
396 |
|
T17 |
2 |
lower_val |
270924 |
1 |
|
|
T2 |
58 |
|
T3 |
352 |
|
T17 |
8 |
zero_val |
155414 |
1 |
|
|
T2 |
124 |
|
T17 |
8 |
|
T33 |
240 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
48240 |
1 |
|
|
T3 |
97 |
|
T7 |
32 |
|
T19 |
33 |
higher_val |
higher_val |
auto[1] |
19171 |
1 |
|
|
T2 |
18 |
|
T17 |
1 |
|
T33 |
25 |
higher_val |
lower_val |
auto[0] |
48341 |
1 |
|
|
T3 |
97 |
|
T17 |
1 |
|
T7 |
37 |
higher_val |
lower_val |
auto[1] |
19308 |
1 |
|
|
T2 |
20 |
|
T33 |
32 |
|
T34 |
260 |
higher_val |
zero_val |
auto[0] |
80 |
1 |
|
|
T36 |
1 |
|
T18 |
1 |
|
T42 |
1 |
higher_val |
zero_val |
auto[1] |
38705 |
1 |
|
|
T2 |
26 |
|
T17 |
2 |
|
T33 |
62 |
lower_val |
higher_val |
auto[0] |
47760 |
1 |
|
|
T3 |
109 |
|
T7 |
43 |
|
T34 |
1 |
lower_val |
higher_val |
auto[1] |
19256 |
1 |
|
|
T2 |
20 |
|
T33 |
22 |
|
T34 |
287 |
lower_val |
lower_val |
auto[0] |
48643 |
1 |
|
|
T3 |
73 |
|
T7 |
49 |
|
T19 |
32 |
lower_val |
lower_val |
auto[1] |
19028 |
1 |
|
|
T2 |
11 |
|
T17 |
3 |
|
T33 |
34 |
lower_val |
zero_val |
auto[0] |
90 |
1 |
|
|
T39 |
1 |
|
T162 |
1 |
|
T210 |
1 |
lower_val |
zero_val |
auto[1] |
38485 |
1 |
|
|
T2 |
37 |
|
T17 |
3 |
|
T33 |
62 |
zero_val |
higher_val |
auto[0] |
609 |
1 |
|
|
T3 |
1 |
|
T34 |
1 |
|
T8 |
2 |
zero_val |
higher_val |
auto[1] |
152 |
1 |
|
|
T34 |
1 |
|
T35 |
1 |
|
T211 |
1 |
zero_val |
lower_val |
auto[0] |
577 |
1 |
|
|
T17 |
1 |
|
T7 |
1 |
|
T19 |
1 |
zero_val |
lower_val |
auto[1] |
117 |
1 |
|
|
T35 |
2 |
|
T36 |
1 |
|
T199 |
1 |
zero_val |
zero_val |
auto[0] |
238 |
1 |
|
|
T2 |
1 |
|
T33 |
1 |
|
T35 |
1 |
zero_val |
zero_val |
auto[1] |
176 |
1 |
|
|
T2 |
2 |
|
T34 |
1 |
|
T35 |
5 |