Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100955447	1			T2	14774		T3	209224		T17	271
all_pins[1]	100955447	1			T2	14774		T3	209224		T17	271
all_pins[2]	100955447	1			T2	14774		T3	209224		T17	271

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	302027469	1			T2	29498		T3	627122		T17	800
values[0x1]	838872	1			T2	14824		T3	550		T17	13
transitions[0x0=>0x1]	836603	1			T2	14726		T3	550		T17	13
transitions[0x1=>0x0]	836624	1			T2	14727		T3	550		T17	13

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100445191	1			T2	14626		T3	208674		T17	258
all_pins[0]	values[0x1]	510256	1			T2	148		T3	550		T17	13
all_pins[0]	transitions[0x0=>0x1]	510239	1			T2	148		T3	550		T17	13
all_pins[0]	transitions[0x1=>0x0]	6314	1			T19	69		T41	23		T199	1
all_pins[1]	values[0x0]	100949116	1			T2	14774		T3	209224		T17	271
all_pins[1]	values[0x1]	6331	1			T19	69		T41	23		T199	1
all_pins[1]	transitions[0x0=>0x1]	6069	1			T19	69		T41	23		T199	1
all_pins[1]	transitions[0x1=>0x0]	322023	1			T2	14676		T20	217		T15	6341
all_pins[2]	values[0x0]	100633162	1			T2	98		T3	209224		T17	271
all_pins[2]	values[0x1]	322285	1			T2	14676		T20	217		T15	6351
all_pins[2]	transitions[0x0=>0x1]	320295	1			T2	14578		T20	217		T15	6308
all_pins[2]	transitions[0x1=>0x0]	508287	1			T2	51		T3	550		T17	13