Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10796673 |
1 |
|
|
T2 |
17462 |
|
T3 |
2992 |
|
T17 |
96 |
auto[1] |
10796657 |
1 |
|
|
T2 |
17462 |
|
T3 |
2992 |
|
T17 |
96 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21354122 |
1 |
|
|
T2 |
34776 |
|
T3 |
5984 |
|
T17 |
192 |
triple_byte_access |
79744 |
1 |
|
|
T2 |
44 |
|
T7 |
66 |
|
T34 |
620 |
halfword_access |
80032 |
1 |
|
|
T2 |
60 |
|
T7 |
66 |
|
T34 |
632 |
byte_access |
79432 |
1 |
|
|
T2 |
44 |
|
T7 |
46 |
|
T34 |
620 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10677069 |
1 |
|
|
T2 |
17388 |
|
T3 |
2992 |
|
T17 |
96 |
auto[0] |
triple_byte_access |
39872 |
1 |
|
|
T2 |
22 |
|
T7 |
33 |
|
T34 |
310 |
auto[0] |
halfword_access |
40016 |
1 |
|
|
T2 |
30 |
|
T7 |
33 |
|
T34 |
316 |
auto[0] |
byte_access |
39716 |
1 |
|
|
T2 |
22 |
|
T7 |
23 |
|
T34 |
310 |
auto[1] |
word_access |
10677053 |
1 |
|
|
T2 |
17388 |
|
T3 |
2992 |
|
T17 |
96 |
auto[1] |
triple_byte_access |
39872 |
1 |
|
|
T2 |
22 |
|
T7 |
33 |
|
T34 |
310 |
auto[1] |
halfword_access |
40016 |
1 |
|
|
T2 |
30 |
|
T7 |
33 |
|
T34 |
316 |
auto[1] |
byte_access |
39716 |
1 |
|
|
T2 |
22 |
|
T7 |
23 |
|
T34 |
310 |