Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98973314	1			T1	1882		T2	157906		T3	292
all_values[1]	98973314	1			T1	1882		T2	157906		T3	292
all_values[2]	98973314	1			T1	1882		T2	157906		T3	292

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

537484

1

T2

4574

T3

18

T37

119

auto[1]

296382458

1

T1

5646

T2

469144

T3

858

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295409058

1

T1

4839

T2

473280

T3

840

auto[1]

1510884

1

T1

807

T2

438

T3

36

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	181104	1			T2	4570		T37	8		T40	1
all_values[0]	auto[0]	auto[1]	2052	1			T2	4		T37	2		T40	2
all_values[0]	auto[1]	auto[0]	98288582	1			T1	1613		T2	153190		T3	280
all_values[0]	auto[1]	auto[1]	501576	1			T1	269		T2	142		T3	12
all_values[1]	auto[0]	auto[0]	194958	1			T3	16		T40	4		T42	21
all_values[1]	auto[0]	auto[1]	1571	1			T3	2		T40	3		T42	4
all_values[1]	auto[1]	auto[0]	98274728	1			T1	1613		T2	157760		T3	264
all_values[1]	auto[1]	auto[1]	502057	1			T1	269		T2	146		T3	10
all_values[2]	auto[0]	auto[0]	156300	1			T37	100		T38	4		T40	1
all_values[2]	auto[0]	auto[1]	1499	1			T37	9		T38	3		T40	2
all_values[2]	auto[1]	auto[0]	98313386	1			T1	1613		T2	157760		T3	280
all_values[2]	auto[1]	auto[1]	502129	1			T1	269		T2	146		T3	12