Summary for Variable entropy_fast_process
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_fast_process
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170507 |
1 |
|
|
T1 |
95 |
|
T2 |
56 |
|
T3 |
3 |
auto[1] |
170389 |
1 |
|
|
T1 |
84 |
|
T2 |
39 |
|
T3 |
6 |
Summary for Variable entropy_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
3 |
1 |
2 |
66.67 |
Automatically Generated Bins for entropy_mode
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[EntropyModeNone] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[EntropyModeEdn] |
169471 |
1 |
|
|
T3 |
9 |
|
T37 |
23 |
|
T38 |
374 |
auto[EntropyModeSw] |
171425 |
1 |
|
|
T1 |
179 |
|
T2 |
95 |
|
T40 |
2265 |
Summary for Variable key_len
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for key_len
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[Key128] |
65130 |
1 |
|
|
T1 |
34 |
|
T2 |
24 |
|
T37 |
6 |
auto[Key192] |
65165 |
1 |
|
|
T1 |
39 |
|
T2 |
16 |
|
T37 |
1 |
auto[Key256] |
79771 |
1 |
|
|
T1 |
32 |
|
T2 |
12 |
|
T3 |
9 |
auto[Key384] |
65237 |
1 |
|
|
T1 |
32 |
|
T2 |
22 |
|
T37 |
7 |
auto[Key512] |
65593 |
1 |
|
|
T1 |
42 |
|
T2 |
21 |
|
T37 |
3 |
Summary for Variable kmac_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
309186 |
1 |
|
|
T1 |
43 |
|
T2 |
25 |
|
T37 |
4 |
auto[1] |
31710 |
1 |
|
|
T1 |
136 |
|
T2 |
70 |
|
T3 |
9 |
Summary for Variable mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
3 |
0 |
3 |
100.00 |
Automatically Generated Bins for mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[Sha3] |
66808 |
1 |
|
|
T1 |
23 |
|
T2 |
3 |
|
T38 |
374 |
auto[Shake] |
239135 |
1 |
|
|
T1 |
20 |
|
T2 |
22 |
|
T37 |
4 |
auto[CShake] |
34953 |
1 |
|
|
T1 |
136 |
|
T2 |
70 |
|
T3 |
9 |
Summary for Variable msg_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for msg_endian
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170451 |
1 |
|
|
T1 |
97 |
|
T2 |
48 |
|
T3 |
7 |
auto[1] |
170445 |
1 |
|
|
T1 |
82 |
|
T2 |
47 |
|
T3 |
2 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
330689 |
1 |
|
|
T1 |
179 |
|
T2 |
95 |
|
T3 |
9 |
auto[1] |
10207 |
1 |
|
|
T7 |
2 |
|
T21 |
121 |
|
T8 |
25 |
Summary for Variable state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_endian
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170656 |
1 |
|
|
T1 |
87 |
|
T2 |
48 |
|
T3 |
5 |
auto[1] |
170240 |
1 |
|
|
T1 |
92 |
|
T2 |
47 |
|
T3 |
4 |
Summary for Variable strength
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for strength
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[L128] |
136428 |
1 |
|
|
T1 |
84 |
|
T2 |
52 |
|
T3 |
6 |
auto[L224] |
19438 |
1 |
|
|
T1 |
6 |
|
T2 |
1 |
|
T48 |
1 |
auto[L256] |
156640 |
1 |
|
|
T1 |
78 |
|
T2 |
41 |
|
T3 |
3 |
auto[L384] |
15788 |
1 |
|
|
T1 |
5 |
|
T43 |
1 |
|
T45 |
310 |
auto[L512] |
12602 |
1 |
|
|
T1 |
6 |
|
T2 |
1 |
|
T39 |
246 |
Summary for Variable xof_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for xof_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
322901 |
1 |
|
|
T1 |
94 |
|
T2 |
53 |
|
T37 |
10 |
auto[1] |
17995 |
1 |
|
|
T1 |
85 |
|
T2 |
42 |
|
T3 |
9 |
Summary for Cross kmac_cross
Samples crossed: kmac_en xof_en strength key_len msg_endian state_endian entropy_mode entropy_fast_process
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for kmac_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
31710 |
1 |
|
|
T1 |
136 |
|
T2 |
70 |
|
T3 |
9 |
Summary for Cross cshake_cross
Samples crossed: mode strength msg_endian state_endian entropy_mode entropy_fast_process
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for cshake_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
34953 |
1 |
|
|
T1 |
136 |
|
T2 |
70 |
|
T3 |
9 |
Summary for Cross shake_cross
Samples crossed: mode strength msg_endian state_endian entropy_mode entropy_fast_process
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for shake_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
239135 |
1 |
|
|
T1 |
20 |
|
T2 |
22 |
|
T37 |
4 |
Summary for Cross sha3_cross
Samples crossed: mode strength msg_endian state_endian entropy_mode entropy_fast_process
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for sha3_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
66808 |
1 |
|
|
T1 |
23 |
|
T2 |
3 |
|
T38 |
374 |