Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
345630 |
1 |
|
|
T1 |
358 |
|
T2 |
190 |
|
T3 |
2 |
auto[1] |
339162 |
1 |
|
|
T3 |
16 |
|
T37 |
44 |
|
T38 |
746 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
171052 |
1 |
|
|
T1 |
92 |
|
T2 |
45 |
|
T3 |
6 |
lower_val |
168739 |
1 |
|
|
T1 |
88 |
|
T2 |
44 |
|
T3 |
7 |
zero_val |
1804 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
257140 |
1 |
|
|
T1 |
176 |
|
T2 |
78 |
|
T3 |
6 |
lower_val |
257768 |
1 |
|
|
T1 |
182 |
|
T2 |
112 |
|
T3 |
4 |
zero_val |
169884 |
1 |
|
|
T3 |
8 |
|
T37 |
26 |
|
T38 |
370 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43028 |
1 |
|
|
T1 |
46 |
|
T2 |
17 |
|
T40 |
655 |
higher_val |
higher_val |
auto[1] |
21042 |
1 |
|
|
T3 |
2 |
|
T37 |
5 |
|
T38 |
44 |
higher_val |
lower_val |
auto[0] |
43316 |
1 |
|
|
T1 |
46 |
|
T2 |
28 |
|
T40 |
594 |
higher_val |
lower_val |
auto[1] |
21225 |
1 |
|
|
T3 |
1 |
|
T37 |
2 |
|
T38 |
54 |
higher_val |
zero_val |
auto[0] |
78 |
1 |
|
|
T117 |
1 |
|
T19 |
1 |
|
T72 |
1 |
higher_val |
zero_val |
auto[1] |
42363 |
1 |
|
|
T3 |
3 |
|
T37 |
3 |
|
T38 |
96 |
lower_val |
higher_val |
auto[0] |
42424 |
1 |
|
|
T1 |
42 |
|
T2 |
15 |
|
T3 |
1 |
lower_val |
higher_val |
auto[1] |
20878 |
1 |
|
|
T3 |
1 |
|
T37 |
2 |
|
T38 |
63 |
lower_val |
lower_val |
auto[0] |
42869 |
1 |
|
|
T1 |
46 |
|
T2 |
29 |
|
T40 |
556 |
lower_val |
lower_val |
auto[1] |
20859 |
1 |
|
|
T3 |
2 |
|
T37 |
4 |
|
T38 |
33 |
lower_val |
zero_val |
auto[0] |
81 |
1 |
|
|
T115 |
1 |
|
T48 |
1 |
|
T16 |
1 |
lower_val |
zero_val |
auto[1] |
41628 |
1 |
|
|
T3 |
3 |
|
T37 |
4 |
|
T38 |
100 |
zero_val |
higher_val |
auto[0] |
554 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T38 |
1 |
zero_val |
higher_val |
auto[1] |
123 |
1 |
|
|
T41 |
1 |
|
T117 |
2 |
|
T205 |
2 |
zero_val |
lower_val |
auto[0] |
577 |
1 |
|
|
T2 |
1 |
|
T40 |
3 |
|
T7 |
1 |
zero_val |
lower_val |
auto[1] |
111 |
1 |
|
|
T153 |
1 |
|
T205 |
2 |
|
T16 |
3 |
zero_val |
zero_val |
auto[0] |
236 |
1 |
|
|
T37 |
1 |
|
T39 |
1 |
|
T46 |
1 |
zero_val |
zero_val |
auto[1] |
203 |
1 |
|
|
T41 |
1 |
|
T153 |
1 |
|
T117 |
4 |