Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98973314	1			T1	1882		T2	157906		T3	292
all_pins[1]	98973314	1			T1	1882		T2	157906		T3	292
all_pins[2]	98973314	1			T1	1882		T2	157906		T3	292

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	296139404	1			T1	5377		T2	473543		T3	864
values[0x1]	780538	1			T1	269		T2	175		T3	12
transitions[0x0=>0x1]	778640	1			T1	269		T2	175		T3	12
transitions[0x1=>0x0]	778664	1			T1	269		T2	175		T3	12

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98471738	1			T1	1613		T2	157764		T3	280
all_pins[0]	values[0x1]	501576	1			T1	269		T2	142		T3	12
all_pins[0]	transitions[0x0=>0x1]	501560	1			T1	269		T2	142		T3	12
all_pins[0]	transitions[0x1=>0x0]	5144	1			T2	33		T41	30		T42	2
all_pins[1]	values[0x0]	98968154	1			T1	1882		T2	157873		T3	292
all_pins[1]	values[0x1]	5160	1			T2	33		T41	30		T42	2
all_pins[1]	transitions[0x0=>0x1]	4925	1			T2	33		T41	30		T42	2
all_pins[1]	transitions[0x1=>0x0]	273567	1			T22	20		T16	3651		T25	968
all_pins[2]	values[0x0]	98699512	1			T1	1882		T2	157906		T3	292
all_pins[2]	values[0x1]	273802	1			T22	20		T16	3657		T25	968
all_pins[2]	transitions[0x0=>0x1]	272155	1			T22	20		T16	3638		T25	967
all_pins[2]	transitions[0x1=>0x0]	499953	1			T1	269		T2	142		T3	12