Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	657	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5328	1			T2	13		T37	4		T7	5
len_601_800	12265	1			T2	34		T37	11		T7	3
len_401_600	7961	1			T2	19		T37	4		T7	3
len_201_400	16312	1			T2	9		T37	4		T40	251
len_65_200	72822	1			T1	82		T2	9		T40	680
len_min_for_xof_require_squeeze	990	1			T40	10		T117	9		T119	9
len_keccak_block_sizes[72]	743	1			T1	2		T40	5		T117	9
len_keccak_block_sizes[104]	743	1			T1	2		T40	5		T43	1
len_keccak_block_sizes[136]	737	1			T1	3		T40	5		T47	1
len_keccak_block_sizes[144]	287	1			T1	1		T2	1		T40	5
len_keccak_block_sizes[168]	279	1			T40	5		T206	5		T207	5
len_datapath_width	14032	1			T1	7		T2	1		T3	3
len_2_63	211466	1			T1	90		T2	7		T3	6
len_1	53	1			T208	1		T73	1		T17	1