Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10497423 |
1 |
|
|
T1 |
6257 |
|
T2 |
14857 |
|
T3 |
96 |
auto[1] |
10497377 |
1 |
|
|
T1 |
6257 |
|
T2 |
14857 |
|
T3 |
96 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20760442 |
1 |
|
|
T1 |
12294 |
|
T2 |
29574 |
|
T3 |
192 |
triple_byte_access |
77912 |
1 |
|
|
T1 |
78 |
|
T2 |
44 |
|
T37 |
14 |
halfword_access |
78444 |
1 |
|
|
T1 |
62 |
|
T2 |
52 |
|
T37 |
14 |
byte_access |
78002 |
1 |
|
|
T1 |
80 |
|
T2 |
44 |
|
T37 |
14 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10380244 |
1 |
|
|
T1 |
6147 |
|
T2 |
14787 |
|
T3 |
96 |
auto[0] |
triple_byte_access |
38956 |
1 |
|
|
T1 |
39 |
|
T2 |
22 |
|
T37 |
7 |
auto[0] |
halfword_access |
39222 |
1 |
|
|
T1 |
31 |
|
T2 |
26 |
|
T37 |
7 |
auto[0] |
byte_access |
39001 |
1 |
|
|
T1 |
40 |
|
T2 |
22 |
|
T37 |
7 |
auto[1] |
word_access |
10380198 |
1 |
|
|
T1 |
6147 |
|
T2 |
14787 |
|
T3 |
96 |
auto[1] |
triple_byte_access |
38956 |
1 |
|
|
T1 |
39 |
|
T2 |
22 |
|
T37 |
7 |
auto[1] |
halfword_access |
39222 |
1 |
|
|
T1 |
31 |
|
T2 |
26 |
|
T37 |
7 |
auto[1] |
byte_access |
39001 |
1 |
|
|
T1 |
40 |
|
T2 |
22 |
|
T37 |
7 |