Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100546293	1			T1	214343		T2	17265		T3	6
all_values[1]	100546293	1			T1	214343		T2	17265		T3	6
all_values[2]	100546293	1			T1	214343		T2	17265		T3	6

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

541967

1

T1

12

T2

309

T3

12

auto[1]

301096912

1

T1

643017

T2

51486

T3

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300100245

1

T1

641403

T2

51315

T3

18

auto[1]

1538634

1

T1

1626

T2

480

T7

1926

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	167930	1			T3	6		T7	1789		T34	48
all_values[0]	auto[0]	auto[1]	1979	1			T7	18		T34	10		T8	2
all_values[0]	auto[1]	auto[0]	99865485	1			T1	213801		T2	17105		T7	116125
all_values[0]	auto[1]	auto[1]	510899	1			T1	542		T2	160		T7	624
all_values[1]	auto[0]	auto[0]	193834	1			T7	5418		T34	38		T8	1
all_values[1]	auto[0]	auto[1]	1514	1			T7	21		T34	8		T9	2
all_values[1]	auto[1]	auto[0]	99839581	1			T1	213801		T2	17105		T3	6
all_values[1]	auto[1]	auto[1]	511364	1			T1	542		T2	160		T7	621
all_values[2]	auto[0]	auto[0]	175199	1			T1	7		T2	306		T3	6
all_values[2]	auto[0]	auto[1]	1511	1			T1	5		T2	3		T7	11
all_values[2]	auto[1]	auto[0]	99858216	1			T1	213794		T2	16799		T7	111895
all_values[2]	auto[1]	auto[1]	511367	1			T1	537		T2	157		T7	631