Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
365138 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
332930 |
1 |
|
|
T1 |
746 |
|
T2 |
216 |
|
T7 |
432 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174662 |
1 |
|
|
T1 |
180 |
|
T2 |
32 |
|
T3 |
1 |
lower_val |
173162 |
1 |
|
|
T1 |
171 |
|
T2 |
94 |
|
T7 |
227 |
zero_val |
1752 |
1 |
|
|
T1 |
3 |
|
T2 |
3 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
264292 |
1 |
|
|
T1 |
174 |
|
T2 |
64 |
|
T7 |
354 |
lower_val |
266270 |
1 |
|
|
T1 |
170 |
|
T2 |
54 |
|
T3 |
2 |
zero_val |
167506 |
1 |
|
|
T1 |
404 |
|
T2 |
100 |
|
T7 |
218 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45538 |
1 |
|
|
T7 |
62 |
|
T35 |
567 |
|
T20 |
38 |
higher_val |
higher_val |
auto[1] |
20617 |
1 |
|
|
T1 |
46 |
|
T2 |
10 |
|
T7 |
26 |
higher_val |
lower_val |
auto[0] |
45599 |
1 |
|
|
T3 |
1 |
|
T7 |
53 |
|
T35 |
543 |
higher_val |
lower_val |
auto[1] |
21052 |
1 |
|
|
T1 |
41 |
|
T2 |
5 |
|
T7 |
28 |
higher_val |
zero_val |
auto[0] |
73 |
1 |
|
|
T7 |
5 |
|
T9 |
1 |
|
T116 |
1 |
higher_val |
zero_val |
auto[1] |
41783 |
1 |
|
|
T1 |
93 |
|
T2 |
17 |
|
T7 |
61 |
lower_val |
higher_val |
auto[0] |
45023 |
1 |
|
|
T7 |
51 |
|
T35 |
570 |
|
T20 |
49 |
lower_val |
higher_val |
auto[1] |
20537 |
1 |
|
|
T1 |
28 |
|
T2 |
24 |
|
T7 |
27 |
lower_val |
lower_val |
auto[0] |
45453 |
1 |
|
|
T7 |
69 |
|
T35 |
554 |
|
T20 |
49 |
lower_val |
lower_val |
auto[1] |
20479 |
1 |
|
|
T1 |
35 |
|
T2 |
23 |
|
T7 |
25 |
lower_val |
zero_val |
auto[0] |
72 |
1 |
|
|
T7 |
1 |
|
T22 |
1 |
|
T142 |
1 |
lower_val |
zero_val |
auto[1] |
41598 |
1 |
|
|
T1 |
108 |
|
T2 |
47 |
|
T7 |
54 |
zero_val |
higher_val |
auto[0] |
524 |
1 |
|
|
T7 |
3 |
|
T35 |
2 |
|
T20 |
1 |
zero_val |
higher_val |
auto[1] |
133 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
zero_val |
lower_val |
auto[0] |
527 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T35 |
1 |
zero_val |
lower_val |
auto[1] |
130 |
1 |
|
|
T2 |
1 |
|
T7 |
4 |
|
T39 |
2 |
zero_val |
zero_val |
auto[0] |
241 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T9 |
1 |
zero_val |
zero_val |
auto[1] |
197 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T85 |
2 |