Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hash_mode	3	0	3	100.00	100	1	1	0
kmac_mode	2	0	2	100.00	100	1	1	2
msgfifo_depth	11	0	11	100.00	100	1	1	0
msgfifo_empty	2	0	2	100.00	100	1	1	2
msgfifo_full	2	0	2	100.00	100	1	1	2

Summary for Variable hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	16770854	1			T2	29239		T3	5		T7	163015
shake	57521703	1			T2	7056		T7	53867		T35	461087
sha3	35305913	1			T1	213594		T2	532		T7	951

---

Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92826563

1

T1

213594

T2

7588

T7

54816

auto[1]

16771907

1

T2

29239

T3

5

T7

163017

---

Summary for Variable msgfifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for msgfifo_depth

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
depth[0x00]	93289503	1			T1	159003		T2	29954		T3	2
depth[0x01]	3619639	1			T1	12364		T2	1019		T3	2
depth[0x02]	3141777	1			T1	13652		T2	998		T3	1
depth[0x03]	2940752	1			T1	12838		T2	984		T7	10583
depth[0x04]	2637351	1			T1	10879		T2	875		T7	8844
depth[0x05]	1537556	1			T1	4857		T2	570		T7	7174
depth[0x06]	497263	1			T1	1		T2	205		T7	5199
depth[0x07]	408136	1			T2	204		T7	3944		T20	274
depth[0x08]	397782	1			T2	237		T7	4116		T20	352
depth[0x09]	376859	1			T2	200		T7	3806		T20	286
depth[0x0a]	751852	1			T2	1581		T7	9534		T20	2506

---

Summary for Variable msgfifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16308967

1

T1

54591

T2

6873

T3

3

auto[1]

93289503

1

T1

159003

T2

29954

T3

2

---

Summary for Variable msgfifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108846618

1

T1

213594

T2

35246

T3

5

auto[1]

751852

1

T2

1581

T7

9534

T20

2506